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Release 7.1.01i ngdbuild H.39 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -intstyle ise -dd e:\demo_fpga/_ngo -nt timestamp -uc top_fpga.ucf -p xc2s100e-pq208-6

PROGRAM=PAR STATE=ROUTED TIMESPECS_MET=OFF

-------------------------------------------------------------------------------- Release 7.1.01i Trace H.39 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. E:/Program/EDA/Xilinx/bin/nt

set -tmpdir __projnav set -xsthdpdir ./xst run -ifn top_fpga_demo.prj -ifmt mixed -ofn top_fpga_demo -ofmt NGC -p xc2s100e-6-pq208 -top top_fpga_demo -opt_mode Speed -opt_level 1 -iuc NO -

# XST flow : Creating project file mem_inform.prj # xst flow : RunXST mem_inform.prj __projnav/mem_inform.xst ./xst # XST flow : Creating project file mem_inform.prj # xst flow : RunXST mem_i

Release 7.1.01i par H.39 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. HXS:: Fri Mar 25 06:54:52 2005 par -w -intstyle ise -ol std -t 1 top_fpga_demo_map.ncd top_fpga_demo.ncd top_fpg

-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 22:22:03 03/23/05 -- Design Name: -- Module Name: Top_FPGA