top_fpga_demo.twr

总体演示程序DEMO_FPGA.rar

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Release 7.1.01i Trace H.39
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

E:/Program/EDA/Xilinx/bin/nt/trce.exe -ise e:\demo_fpga\DEMO_FPGA.ise -intstyle
ise -e 3 -l 3 -s 6 -xml top_fpga_demo top_fpga_demo.ncd -o top_fpga_demo.twr
top_fpga_demo.pcf


Design file:              top_fpga_demo.ncd
Physical constraint file: top_fpga_demo.pcf
Device,speed:             xc2s100e,-6 (PRODUCTION 1.18 2005-01-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
button<0>   |   10.560(R)|   -2.016(R)|clk_BUFGP         |   0.000|
button<1>   |   10.228(R)|   -2.343(R)|clk_BUFGP         |   0.000|
button<2>   |   10.305(R)|   -2.218(R)|clk_BUFGP         |   0.000|
button<3>   |    9.739(R)|   -2.139(R)|clk_BUFGP         |   0.000|
itclk       |    9.068(R)|   -2.991(R)|clk_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
lcden       |   12.763(R)|clk_BUFGP         |   0.000|
tone        |   12.335(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |   13.040|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Fri Mar 25 06:55:13 2005
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Peak Memory Usage: 76 MB