top_fpga_demo.par

总体演示程序DEMO_FPGA.rar

Release 7.1.01i par H.39
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

HXS::  Fri Mar 25 06:54:52 2005

par -w -intstyle ise -ol std -t 1 top_fpga_demo_map.ncd top_fpga_demo.ncd
top_fpga_demo.pcf 


Constraints file: top_fpga_demo.pcf.
Loading device for application Rf_Device from file '2s100e.nph' in environment
E:/Program/EDA/Xilinx.
   "top_fpga_demo" is an NCD, version 3.1, device xc2s100e, package pq208, speed
-6

Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 85.000
Celsius)
Initializing voltage to 1.700 Volts. (default - Range: 1.700 to 1.900 Volts)


Device speed data version:  "PRODUCTION 1.18 2005-01-22".


Device Utilization Summary:

   Number of BLOCKRAMs                 2 out of 10     20%
   Number of GCLKs                     3 out of 4      75%
   Number of External GCLKIOBs         1 out of 4      25%
      Number of LOCed GCLKIOBs         1 out of 1     100%

   Number of External IOBs            40 out of 142    28%
      Number of LOCed IOBs            40 out of 40    100%

   Number of SLICEs                  464 out of 1200   38%


Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98a8f7) REAL time: 2 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.23
Phase 3.23 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 2 secs 

Phase 6.8
................................................
Phase 6.8 (Checksum:a3e0ed) REAL time: 3 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 3 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 4 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 4 secs 

Writing design to file top_fpga_demo.ncd


Total REAL time to Placer completion: 4 secs 
Total CPU time to Placer completion: 4 secs 

Starting Router

Phase 1: 2980 unrouted;       REAL time: 5 secs 

Phase 2: 2705 unrouted;       REAL time: 11 secs 

Phase 3: 672 unrouted;       REAL time: 13 secs 

Phase 4: 0 unrouted;       REAL time: 14 secs 

Total REAL time to Router completion: 14 secs 
Total CPU time to Router completion: 13 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|               clk1k |      GCLKBUF1| No   |   67 |  0.279     |  0.542      |
+---------------------+--------------+------+------+------------+-------------+
|           reg_clk1k |      GCLKBUF3| No   |   85 |  0.141     |  0.513      |
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP |      GCLKBUF0| No   |   53 |  0.061     |  0.416      |
+---------------------+--------------+------+------+------------+-------------+
|           u8/_n0001 |      Low-Skew|      |    8 |  0.198     |  4.824      |
+---------------------+--------------+------+------+------------+-------------+
|         u4/u0/sclkb |         Local|      |    6 |  2.747     |  3.483      |
+---------------------+--------------+------+------+------------+-------------+
|         u4/u0/sclka |         Local|      |    5 |  0.141     |  3.365      |
+---------------------+--------------+------+------+------------+-------------+
|        u5/u0/_n0001 |         Local|      |    7 |  2.380     |  3.863      |
+---------------------+--------------+------+------+------------+-------------+
|        u4/u1/_n0001 |         Local|      |    5 |  0.102     |  3.685      |
+---------------------+--------------+------+------+------------+-------------+
|                clk1 |         Local|      |    6 |  0.771     |  3.437      |
+---------------------+--------------+------+------+------------+-------------+

INFO:Par:340 - 
   The Delay report will not be generated when running non-timing driven PAR
   with effort level Standard or Medium. If a delay report is required please do
   one of the following:  1) use effort level High, 2) use the following
   environment variable "XIL_PAR_GENERATE_DLY_REPORT", 3) create Timing
   constraints for the design.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 15 secs 
Total CPU time to PAR completion: 14 secs 

Peak Memory Usage:  78 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file top_fpga_demo.ncd



PAR done!