top_fpga_demo.vhd

总体演示程序DEMO_FPGA.rar

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-- Company: 
-- Engineer:
--
-- Create Date:    22:22:03 03/23/05
-- Design Name:    
-- Module Name:    Top_FPGA_demo - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Top_FPGA_demo is
     Port (clk : in std_logic;						--50m系统时钟
           -------------------------
           ienter : in std_logic;
           istepa : in std_logic;
           istepb : in std_logic;
           ichose : in std_logic;
           ireset : in std_logic;
		 -------------------------
		 button : in std_logic_vector(3 downto 0);
		 --------------------------
		 tone : out std_logic;
		 -----------------------
		 itclk : in std_logic;
		 otclk : out std_logic;
		 -----------------------
           lcdda : out std_logic;
           lcdrw : out std_logic;
           lcden : out std_logic;
           dout_lcd  : out std_logic_vector(7 downto 0);
		 ----------------------------
		 din_adc : in std_logic;
		 clk_tlc549 : out std_logic;
           cs_tlc549  : out std_logic;	
		 shift      : out std_logic_vector(3 downto 0);			
		 cs_led     : out std_logic_vector(1 downto 0);
		 dout_led   : out std_logic_vector(7 downto 0));

end Top_FPGA_demo;

architecture Behavioral of Top_FPGA_demo is
component page_information
   port (
	     addr: IN std_logic_VECTOR(9 downto 0);
	     clk : IN std_logic;
	     dout: OUT std_logic_VECTOR(7 downto 0));
end component;

component lcd
    Port ( clk   : in std_logic;	   --1khz的扫描频率；
           reset : in std_logic;
           lcdda : out std_logic;
           lcdrw : out std_logic;
           lcden : out std_logic;
		 lcd_address : out std_logic_vector(4 downto 0);
	      lcddin : in std_logic_vector(7 downto 0);
           data  : out std_logic_vector(7 downto 0));
end component;

component keyboards 
    Port ( clk : in std_logic;
           ienter : in std_logic;
           istepa : in std_logic;
           istepb : in std_logic;
           ichose : in std_logic;
           ireset : in std_logic;
		 -----------------------
           oenter : out std_logic;
           ostepa : out std_logic;
           ostepb : out std_logic;
           ochose : out std_logic;
           oreset : out std_logic);
end component;

component page_step
    Port ( clk : in std_logic;    --1khz
           ireset   : in std_logic;
		 ienter   : in std_logic;
           ibuttona : in std_logic;
		 ibuttonb	: in std_logic;
           data :out std_logic_vector(4 downto 0));
end component;

component mode_clk 
    Port ( clk : in std_logic;
           ireset : in std_logic;
           en : in std_logic_vector(4 downto 0);
           addr: in std_logic_vector(4 downto 0);            
           din : in std_logic_vector(7 downto 0);
           dout : out std_logic_vector(7 downto 0));
end component;

component top_mode_cymometer 
    Port ( clka,clkb : std_logic;
           tclk : std_logic;
           en : in std_logic_vector(4 downto 0);
           addr: in std_logic_vector(4 downto 0);            
           din : in std_logic_vector(7 downto 0);
           dout : out std_logic_vector(7 downto 0));
end component;

component electronic_organ 
   port(clk : in std_logic;
        button : in std_logic_vector(3 downto 0);
	   tone : out std_logic);
end component;

component digital_voltmeter 
    Port (clk1k : in std_logic;						--50m系统时钟
		din : in std_logic;
		clk_tlc549 : out std_logic;
          cs_tlc549  : out std_logic;	
		shift      : out std_logic_vector(3 downto 0);			
		cs_led     : out std_logic_vector(1 downto 0);
		dout_led   : out std_logic_vector(7 downto 0);
		dout_lcd   : out std_logic_vector(19 downto 0));
end component;

component page3 
    Port ( en : in std_logic_vector(4 downto 0);
           addr: in std_logic_vector(4 downto 0);            
           din : in std_logic_vector(7 downto 0);
           dint : in std_logic_vector(19 downto 0);
           dout : out std_logic_vector(7 downto 0));
end component;

signal reg_tclk : std_logic;
signal oenter :  std_logic;
signal ostepa :  std_logic;
signal ostepb :  std_logic;
signal ochose :  std_logic;
signal oreset :  std_logic;
signal reg_tone : std_logic;
signal clk1k,clk1 : std_logic;
signal lcd_address : std_logic_vector(4 downto 0);
signal lcddin : std_logic_vector(7 downto 0);
signal addr : std_logic_vector(9 downto 0);
signal reg_cnt : std_logic_vector(4 downto 0);
signal page_d : std_logic_vector(7 downto 0);
signal dout_mode_clk : std_logic_vector(7 downto 0);
signal dout_mode_cymometer : std_logic_vector(7 downto 0);
signal dout_mode_voltage : std_logic_vector(7 downto 0);
signal reg_clk1k : std_logic;
signal dint_vol : std_logic_vector(19 downto 0);

begin
process(clk)
variable cnt : integer range 0 to 50000;
begin
   if rising_edge(clk) then cnt:=cnt+1;
      if cnt<25000 then clk1k<='0';
	 elsif cnt<50000 then clk1k<='1';
	 else cnt:=0;
	 end if;
   end if;
end process;

process(clk1k)
variable cnt : integer range 0 to 1000;
begin
   if rising_edge(clk1k) then cnt:=cnt+1;
      if cnt<500 then clk1<='0';
	 elsif cnt<1000 then clk1<='1';
	 else cnt:=0;
	 end if;
   end if;
end process;
---------------------------------------

---------------------------------------
            addr<=reg_cnt&lcd_address;
---------------------------------------
u0 : page_information port map
                 (addr=>addr,
			   clk=>clk1k,
			   dout=>page_d);

u1 : lcd port map(clk=>clk1k,
                  reset=>oreset,
			   --------------------
                  lcdda=>lcdda,
			   lcdrw=>lcdrw,
			   lcden=>lcden,
			   --------------------
                  lcd_address=>lcd_address,
			   lcddin=>lcddin,
			   data=>dout_lcd);

u2 : keyboards port map(
                  clk=>clk1k,
			   ienter=>ienter,
			   istepa=>istepa,
			   istepb=>istepb,
			   ichose=>ichose,
			   ireset=>ireset,
			   --------------------
			   oenter=>oenter,
			   ostepa=>ostepa,
			   ostepb=>ostepb,
			   ochose=>ochose,
			   oreset=>oreset);

u3 : page_step port map(
                  clk=>clk1k,
			   ireset=>oreset,
			   ienter=>oenter,
			   ibuttona=>ostepa,
			   ibuttonb=>ostepb,
			   data=>reg_cnt);

u4 : mode_clk port map(
                  clk=>clk1,
			   ireset=>oreset,
			   en=>reg_cnt,
			   addr=>lcd_address,
			   din=>page_d,
			   dout=>dout_mode_clk); 

u5 : top_mode_cymometer port map(
                  clka=>clk,
			   clkb=>clk1,
			   tclk=>reg_tclk,
			   en=>reg_cnt,
			   addr=>lcd_address,
			   din=>page_d,
			   dout=>dout_mode_cymometer);
	   ----------------------------
              with reg_cnt select
		    lcddin<=dout_mode_clk when "10001",
		            dout_mode_voltage when "10011",
		            dout_mode_cymometer when "10100",
		            page_d when others;
	   -----------------------------------
		    reg_tclk<=clk1k when ochose='1' else
		              itclk;

              otclk<=clk1;
	   -------------------------------------
u6:electronic_organ port map(
        clk=>clk,
        button=>button,
	   tone=>reg_tone);

	 tone<=reg_tone when reg_cnt="10010" else
		  '1';
	   --------------------------------------

u7:digital_voltmeter port map(
          clk1k=>reg_clk1k,
		din=>din_adc,
		clk_tlc549=>clk_tlc549,
		cs_tlc549=>cs_tlc549,
		shift=>shift,
		cs_led=>cs_led,
		dout_led=>dout_led,
		dout_lcd=>dint_vol);
	   
	     reg_clk1k<=clk1k when reg_cnt="10011" else
		           '0';
u8:page3 port map(
          en=>reg_cnt,
		addr=>lcd_address,
		din=>page_d,
		dint=>dint_vol,
		dout=>dout_mode_voltage);
				 			      
end Behavioral;