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SCHEMATIC START ; // created by map version G.28 on Fri Feb 24 06:52:58 2006 COMP "DIP2K1" LOCATE = SITE "P163" LEVEL 1; COMP "RS" LOCATE = SITE "P166" LEVEL 1; COMP "DB0" LOCATE = SITE "P17

Release 6.2i - ngdbuild G.28 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -intstyle ise -dd f:\trainsilicon\fpgaschool\testcade\fpga40xc200\basic2\lcm\ise\lcm/_n

#PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "DB0" LOC = "P179" ; NET "DB1" LOC = "P181" ; NET "DB2" LOC = "P188" ; NET "DB3" LOC = "P191"

PROGRAM=PAR STATE=ROUTED TIMESPECS_MET=OFF

Release 6.2i Par G.28 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. TOMWANG:: Fri Feb 24 06:52:59 2006 C:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 fpga_lcm_map.ncd fpga_lc

Release 6.2i - Par G.28 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Fri Feb 24 06:53:02 2006 NOTE: This file is designed to be imported into a spreadsheet program such as Microsoft E

# begin LFP file f:\trainsilicon\fpgaschool\testcade\fpga40xc200\basic2\lcm\ise\lcm\fpga_lcm.lfp designfile fpga_lcm.ngd INST "fpga_lcm" COLOR=15 ;

WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net lcm__n0033 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into th

Release 6.2i Map G.28 Xilinx Mapping Report File for Design 'fpga_lcm' Design Information ------------------ Command Line : C:/Xilinx/bin/nt/map.exe -intstyle ise -p xc2s200-pq208-5 -cm area -pr b