fpga_lcm.pcf

来自「清华大学verilog hdl源码例子」· PCF 代码 · 共 17 行

SCHEMATIC START ;
// created by map version G.28 on Fri Feb 24 06:52:58 2006 
COMP "DIP2K1" LOCATE =  SITE "P163" LEVEL 1; 
COMP "RS" LOCATE =  SITE "P166" LEVEL 1; 
COMP "DB0" LOCATE =  SITE "P179" LEVEL 1; 
COMP "DB1" LOCATE =  SITE "P181" LEVEL 1; 
COMP "RW" LOCATE =  SITE "P172" LEVEL 1; 
COMP "DB2" LOCATE =  SITE "P188" LEVEL 1; 
COMP "DB3" LOCATE =  SITE "P191" LEVEL 1; 
COMP "DB4" LOCATE =  SITE "P193" LEVEL 1; 
COMP "DB5" LOCATE =  SITE "P195" LEVEL 1; 
COMP "GCLK0" LOCATE =  SITE "P80" LEVEL 1; 
COMP "DB6" LOCATE =  SITE "P201" LEVEL 1; 
COMP "DB7" LOCATE =  SITE "P203" LEVEL 1; 
COMP "E" LOCATE =  SITE "P174" LEVEL 1; 
SCHEMATIC END ;