fpga_lcm.bld

来自「清华大学verilog hdl源码例子」· BLD 代码 · 共 27 行

BLD
27 行
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Release 6.2i - ngdbuild G.28Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.Command Line: ngdbuild -intstyle ise -dd
f:\trainsilicon\fpgaschool\testcade\fpga40xc200\basic2\lcm\ise\lcm/_ngo -uc
fpga_lcm.ucf -p xc2s200-pq208-5 fpga_lcm.ngc fpga_lcm.ngd Reading NGO file
"f:/trainsilicon/fpgaschool/testcade/fpga40xc200/basic2/lcm/ise/lcm/fpga_lcm.ngc
" ...Reading component libraries for design expansion...Annotating constraints to design from file "fpga_lcm.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary:  Number of errors:     0  Number of warnings:   0Total memory usage is 38076 kilobytesWriting NGD file "fpga_lcm.ngd" ...Writing NGDBUILD log file "fpga_lcm.bld"...

fpga_lcm.bld - 源码说明

本页面展示了「清华大学verilog hdl源码例子」中的 fpga_lcm.bld 源码文件，采用 BLD 编程语言编写，共 27 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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