fpga_lcm.par

清华大学verilog hdl源码例子

Release 6.2i Par G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

TOMWANG::  Fri Feb 24 06:52:59 2006


C:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 fpga_lcm_map.ncd
fpga_lcm.ncd fpga_lcm.pcf 


Constraints file: fpga_lcm.pcf

Loading device database for application Par from file "fpga_lcm_map.ncd".
   "fpga_lcm" is an NCD, version 2.38, device xc2s200, package pq208, speed -5
Loading device for application Par from file 'v200.nph' in environment
C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolved that IOB <DIP2K1> must be placed at site P163.
Resolved that IOB <RS> must be placed at site P166.
Resolved that IOB <DB0> must be placed at site P179.
Resolved that IOB <DB1> must be placed at site P181.
Resolved that IOB <RW> must be placed at site P172.
Resolved that IOB <DB2> must be placed at site P188.
Resolved that IOB <DB3> must be placed at site P191.
Resolved that IOB <DB4> must be placed at site P193.
Resolved that IOB <DB5> must be placed at site P195.
Resolved that GCLKIOB <GCLK0> must be placed at site P80.
Resolved that IOB <DB6> must be placed at site P201.
Resolved that IOB <DB7> must be placed at site P203.
Resolved that IOB <E> must be placed at site P174.


Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            12 out of 140     8%
      Number of LOCed External IOBs   12 out of 12    100%

   Number of SLICEs                   43 out of 2352    1%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989763) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.
Phase 5.8 (Checksum:9f7b0c) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file fpga_lcm.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 216 unrouted;       REAL time: 0 secs 

Phase 2: 200 unrouted;       REAL time: 2 secs 

Phase 3: 51 unrouted;       REAL time: 2 secs 

Phase 4: 0 unrouted;       REAL time: 2 secs 

Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 2 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|       GCLK0_BUFGP          |  Global  |    1   |  0.000     |  0.759      |
+----------------------------+----------+--------+------------+-------------+
|lcm_LCD_state_FFd2          |Low-Skew  |    9   |  0.062     |  5.054      |
+----------------------------+----------+--------+------------+-------------+
|    lcm_cfgcnt<11>          |   Local  |    9   |  0.403     |  4.988      |
+----------------------------+----------+--------+------------+-------------+
|        lcm__n0033          |   Local  |    1   |  0.000     |  2.004      |
+----------------------------+----------+--------+------------+-------------+
|    lcm_delay_counter<0>    |   Local  |    6   |  0.000     |  1.620      |
+----------------------------+----------+--------+------------+-------------+
|    lcm_delay_counter<1>    |   Local  |    6   |  0.000     |  1.077      |
+----------------------------+----------+--------+------------+-------------+
|     lcm_LCD_AC<1>          |   Local  |   10   |  0.000     |  1.561      |
+----------------------------+----------+--------+------------+-------------+
|     lcm_LCD_AC<0>          |   Local  |   10   |  0.000     |  1.156      |
+----------------------------+----------+--------+------------+-------------+
|        lcm__n0032          |   Local  |    5   |  0.116     |  4.406      |
+----------------------------+----------+--------+------------+-------------+
|     lcm_LCD_AC<2>          |   Local  |   10   |  0.000     |  1.157      |
+----------------------------+----------+--------+------------+-------------+
|    lcm_cfgcnt<10>          |   Local  |    2   |  0.000     |  0.890      |
+----------------------------+----------+--------+------------+-------------+
|     lcm_cfgcnt<9>          |   Local  |    2   |  0.000     |  1.410      |
+----------------------------+----------+--------+------------+-------------+
|         lcm_clock          |   Local  |    2   |  0.000     |  0.874      |
+----------------------------+----------+--------+------------+-------------+
|     lcm_cfgcnt<1>          |   Local  |    2   |  0.000     |  1.015      |
+----------------------------+----------+--------+------------+-------------+
|     lcm_cfgcnt<2>          |   Local  |    2   |  0.000     |  1.725      |
+----------------------------+----------+--------+------------+-------------+
|     lcm_cfgcnt<3>          |   Local  |    2   |  0.000     |  1.046      |
+----------------------------+----------+--------+------------+-------------+
|     lcm_cfgcnt<4>          |   Local  |    2   |  0.000     |  1.396      |
+----------------------------+----------+--------+------------+-------------+
|     lcm_cfgcnt<5>          |   Local  |    2   |  0.000     |  1.012      |
+----------------------------+----------+--------+------------+-------------+
|     lcm_cfgcnt<6>          |   Local  |    2   |  0.000     |  1.021      |
+----------------------------+----------+--------+------------+-------------+
|     lcm_cfgcnt<7>          |   Local  |    2   |  0.000     |  1.011      |
+----------------------------+----------+--------+------------+-------------+
|     lcm_cfgcnt<8>          |   Local  |    2   |  0.000     |  1.104      |
+----------------------------+----------+--------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 233


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.704
   The MAXIMUM PIN DELAY IS:                               5.054
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   3.114

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 6.00  d >= 6.00
   ---------   ---------   ---------   ---------   ---------   ---------
          52         117          24           1          22           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 3 secs 
Total CPU time to PAR completion: 2 secs 

Peak Memory Usage:  51 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file fpga_lcm.ncd.


PAR done.