fpga_lcm.ucf

清华大学verilog hdl源码例子

#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments
NET "DB0"  LOC = "P179"  ;
NET "DB1"  LOC = "P181"  ;
NET "DB2"  LOC = "P188"  ;
NET "DB3"  LOC = "P191"  ;
NET "DB4"  LOC = "P193"  ;
NET "DB5"  LOC = "P195"  ;
NET "DB6"  LOC = "P201"  ;
NET "DB7"  LOC = "P203"  ;
NET "DIP2K1"  LOC = "P163"  ;
NET "E"  LOC = "P174"  ;
NET "GCLK0"  LOC = "P80"  ;
NET "RS"  LOC = "P166"  ;
NET "RW"  LOC = "P172"  ;

#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE