代码搜索：FPGA加速
找到约 10,000 项符合「FPGA加速」的源代码
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www.eeworm.com/read/197597/7984793
vhd 条件赋值：使用多路选择器.vhd
-- Conditional Signal Assignment with Multiple Alternatives
-- download from: www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY condsigm IS
PORT
(
www.eeworm.com/read/329969/12922967
rsm lattice.rsm
-inp "getpcmdata_map.ncd" -dir "d:/cpld/fpga/getpcm" -prj "getpcmdata" -gui -touch ngd -lpf "getpcmdata.lpf" -prf "getpcmdata.prf" -msg "Post-Map Design Floorplan"
www.eeworm.com/read/137517/13318020
vhd 条件赋值：使用多路选择器.vhd
-- Conditional Signal Assignment with Multiple Alternatives
-- download from: www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY condsigm IS
PORT
(
www.eeworm.com/read/315669/13538566
v cmos_fifo.v
// cmos_fifo.v
//cmos_fifo_usb.
//use fpga to make a pccamera;befor usb(68013a),
///////////////////////
`timescale 1ns/100ps
module cmos_fifo_usb(
// clk,
www.eeworm.com/read/309739/13665097
txt ram_readme.txt
The following files were generated for 'ram' in directory
D:\Develop\PQS\FPGA\fft_test\fft_test_core\:
ram.edn:
Electronic Data Netlist (EDN) file containing the information
required to i
www.eeworm.com/read/309739/13665112
xco fft.xco
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\Develop\PQS\FPGA\fft_test
SET speedgrade = -4
SET simulationfiles = Structura
www.eeworm.com/read/487908/6501834
vhd 条件赋值：使用多路选择器.vhd
-- Conditional Signal Assignment with Multiple Alternatives
-- download from: www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY condsigm IS
PORT
(
www.eeworm.com/read/157209/11730138
txt 条件赋值：使用多路选择器.txt
-- Conditional Signal Assignment with Multiple Alternatives
-- download from: www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY condsigm IS
PORT
(
www.eeworm.com/read/345513/11810666
transcript
# Reading D:/Program/FPGA_software/ModelSim/tcl/vsim/pref.tcl
# // ModelSim SE 6.2b Jul 31 2006
# //
# // Copyright 2006 Mentor Graphics Corporation
# // All Rights Reserved.
# /
www.eeworm.com/read/257875/11909597
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fpga_a_cc is
generic(
adr_srbuf : integer := 48;
adr_swbuf : integer := 49;
adr_vrbuf_0 : integer := 16;