ram_readme.txt

来自「用vhdl编写的FFT的代码,很全,很强大.」· 文本 代码 · 共 38 行

The following files were generated for 'ram' in directory 
D:\Develop\PQS\FPGA\fft_test\fft_test_core\:

ram.edn:
   Electronic Data Netlist (EDN) file containing the information
   required to implement the module in a Xilinx (R) FPGA.

ram.mif:
   Memory Initialization File which is automatically generated by the
   CORE Generator System for some modules when a simulation flow is
   specified. A MIF data file is used to support HDL functional
   simulation of modules which use arrays of values.

ram.vhd:
   VHDL wrapper file provided to support functional simulation. This
   file contains simulation model customization data that is passed to
   a parameterized simulation model for the core.

ram.vho:
   VHO template file containing code that can be used as a model for
   instantiating a CORE Generator module in a VHDL design.

ram.xco:
   CORE Generator input file containing the parameters used to
   regenerate a core.

ram_flist.txt:
   Text file listing all of the output files produced when a customized
   core was generated in the CORE Generator.

ram_readme.txt:
   Text file indicating the files generated and how they are used.


Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.