📄 cmos_fifo.v
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// cmos_fifo.v
//cmos_fifo_usb.
//use fpga to make a pccamera;befor usb(68013a),
///////////////////////
`timescale 1ns/100ps
module cmos_fifo_usb(
// clk, //fpga clk input;
wclk, //fifo write clk;
// rclk, //fifo read clk;
reset, //fpga reset;
rst, //cmos_fifo reset;
frame_valid,
line_valid,
cmos_data,
rd, //fifo read data;
fifoaddr, //usb fifo addr;
full, //68013 fifo flag,active is high;
empty //68013a fifo flag,active is low;
);
//input clk;
input wclk;
input reset;
input rst;
input full;
input empty;
input frame_valid;
input line_valid;
input [ 7:0] cmos_data;
inout [15:0] rd;
output [ 1:0] fifoaddr;
reg [ 1:0] fifoaddr;
reg [15:0] usbdata;
reg [15:0] rd_out;
reg [ 7:0] wd;
wire [15:0] rdout;
wire [15:0] fifoout;
reg wen;
reg ren;
reg [10:0] waddr;
reg [ 9:0] raddr;
reg [ 7:0] ydata1;
reg [ 7:0] ydata2;
wire [ 7:0] data;
reg inwen;
reg inren;
reg head_en;
reg [3:0] head_count;
reg [6:0] fifo_count;
integer i;
integer data_count;
wire rclk;
wire clk;
wire [15:0] frame_head[6:0];
wire [7:0] proc_data[9:0]; //usb procol
//
reg [3:0] inwaddr;
reg [4:0] inraddr;
reg [7:0] fifodata[9:0];
reg led_control;
parameter[15:0] ledtime = 16'hffff;
reg [15:0] lighttime;
reg clk_div;
assign rdout[ 7:0] = ydata1;
assign rdout[15:8] = ydata2;
assign rclk = wclk;
assign clk = clk_div;
//the head of a frame;
parameter[15:0] headdata1 = 16'h0200,
headdata2 = 16'h55aa,
headdata3 = 16'h8002,
headdata4 = 16'h0000,
headdata5 = 16'h0000,
headdata6 = 16'h0000,
headdata7 = 16'h0000;
assign frame_head[0] = headdata1;
assign frame_head[1] = headdata2;
assign frame_head[2] = headdata3;
assign frame_head[3] = headdata4;
assign frame_head[4] = headdata5;
assign frame_head[5] = headdata6;
assign frame_head[6] = headdata7;
//usb procol
parameter [7:0] usb_fd1 = 8'ha0,
usb_fd2 = 8'ha1,
usb_fd3 = 8'ha2,
usb_fd4 = 8'ha3,
usb_fd5 = 8'ha4,
usb_fd6 = 8'ha5,
usb_fd7 = 8'ha6,
usb_fd8 = 8'ha7,
usb_fd9 = 8'ha8,
usb_fd10 = 8'ha9;
assign proc_data[0] = usb_fd1;
assign proc_data[1] = usb_fd2;
assign proc_data[2] = usb_fd3;
assign proc_data[3] = usb_fd4;
assign proc_data[4] = usb_fd5;
assign proc_data[5] = usb_fd6;
assign proc_data[6] = usb_fd7;
assign proc_data[7] = usb_fd8;
assign proc_data[8] = usb_fd9;
assign proc_data[9] = usb_fd10;
two_port1280x8 u1 (
.WD ( wd ),
.RD ( fifoout ),
.WEN ( wen ),
.REN ( ren ),
.WADDR ( waddr ),
.RADDR ( raddr ),
.WCLK ( wclk ),
.RCLK ( rclk ),
.RESET ( reset )
);
usb_fifo32x16 u2 (
.WD ( usbdata ),
.RD ( data ),
.WEN ( inwen ),
.REN ( inren ),
.WADDR ( inwaddr ),
.RADDR ( inraddr ),
.WCLK ( wclk ),
.RCLK ( rclk ),
.RESET ( reset )
);
assign rd = ( head_en == 1'b1 || ren == 1'b0 ) ? rd_out : 16'hzzzz;
//clk_div
always @( posedge rclk or negedge reset )
begin
if(reset ==1'b0 || rst == 1'b0 )
clk_div <= 1'b0;
else clk_div <= clk_div +1'b1;
end
//test the up edge of frame_valid;
reg frame_valid1;
reg frame_valid2;
always @(posedge wclk or negedge reset)
begin
if(reset ==1'b0 || rst == 1'b0 )
begin
frame_valid1 <= 1'b0;
frame_valid2 <= 1'b0;
end
else begin
frame_valid1 <= frame_valid;
frame_valid2 <= frame_valid1;
end
end
//head_count;
always @( posedge wclk or negedge reset )
begin
if(reset == 1'b0 || rst == 1'b0)
head_count <= 4'h0;
else begin
if( head_en == 1'b1 & full == 1'b0 & head_count <= 4'h6 )
head_count <= head_count + 1'b1;
else begin
if( full == 1'b1 & head_en == 1'b1)
head_count <= head_count;
else if( head_count == 4'h6 )
head_count <= 4'h0;
end
end
end
//head_en;
always @( posedge wclk or negedge reset )
begin
if(reset == 1'b0 || rst == 1'b0)
head_en <= 1'b0;
else begin
if(frame_valid1 ==1'b1 & frame_valid2 == 1'b0 )
head_en <= 1'b1;
else begin
if( head_count == 4'h6 )
head_en <= 1'b0;
end
end
end
//wd
always @( posedge wclk or negedge reset )
begin
if(reset == 1'b0 || rst == 1'b0)
wd <= 8'h00;
else begin
if( frame_valid == 1'b1 & line_valid == 1'b1)
wd <= cmos_data;
else wd <= 8'h00;
end
end
//wen
always @( posedge wclk or negedge reset )
begin
if(reset == 1'b0 || rst == 1'b0)
wen <= 1'b1;
else begin
if( frame_valid == 1'b1 & line_valid == 1'b1)
wen <= 1'b0;
else wen <= 1'b1;
end
end
//waddr
always @( posedge wclk or negedge reset )
begin
if(reset == 1'b0 || rst == 1'b0)
waddr <= 11'h000;
else begin
if( frame_valid == 1'b1 & line_valid == 1'b1)
waddr <= waddr + 1'b1;
else waddr <= 11'h000;
end
end
//raddr
always @( posedge wclk or negedge reset )
begin
if(reset == 1'b0 || rst == 1'b0)
raddr <= 10'h000;
else begin
if( waddr >= 11'h280 & raddr <= 10'h280 & full == 1'b0 ) // ren== 1'b0 & raddr < 10'h280)
raddr <=raddr + 1'b1;
else begin
if( raddr < 10'h280 & full == 1'b1 )
raddr <=raddr;
else if( raddr == 10'h280 )
raddr <= 10'h000;
end
end
end
//ydata1,ydata2
always @( posedge rclk or negedge reset )
begin
if(reset == 1'b0 || rst == 1'b0)
begin
ydata1 <= 8'h00;
ydata2 <= 8'h00;
end
else
begin
ydata1 <= fifoout[7:0];
ydata2 <= ydata1;
end
end
//ren
always @( posedge wclk or negedge reset )
begin
if(reset == 1'b0 || rst == 1'b0)
ren <= 1'b1;
else begin
if( waddr >= 11'h280 & raddr <= 10'h280 & full == 1'b0 )
ren <= 1'b0;
else begin
if(raddr == 10'h280 || full == 1'b1)
ren<= 1'b1;
end
end
end
//rd_out
always @( posedge clk or negedge reset )
begin
if(reset == 1'b0 || rst == 1'b0)
rd_out = 16'h0000;
else begin
if(head_en ==1'b1)
rd_out = frame_head[head_count];
else if(ren == 1'b0)
rd_out = rdout;
end
end
//i
always @( posedge rclk or negedge reset )
begin
if(reset == 1'b0 || rst == 1'b0)
i <= 16'h0000;
else begin
if(head_en ==1'b1)
i <= i+1;
else i <=0;
end
end
//fifoaddr
always @( posedge rclk or negedge reset )
begin
if(reset == 1'b0 || rst == 1'b0)
fifoaddr <= 2'b00;
else begin
if(ren ==1'b0 || head_en ==1'b1)
fifoaddr <= 2'b10;
else fifoaddr <= 2'b00;
end
end
// usb_data
always @( posedge wclk or negedge reset )
begin
if(reset == 1'b0 || rst == 1'b0)
usbdata <=16'h0000;
else begin
if( fifoaddr == 2'b00 & empty == 1'b1 )
usbdata <= rd;
else usbdata <= 16'h0000;
end
end
//inwen
always @( posedge wclk or negedge reset )
begin
if (reset == 1'b0 || rst == 1'b0)
inwen <= 1'b1;
else begin
if( fifoaddr == 2'b00 & empty == 1'b1 & inwaddr <= 4'h04 )
inwen <= 1'b0;
else inwen <= 1'b1;
end
end
//inwaddr
always @( posedge wclk or negedge reset )
begin
if (reset == 1'b0 || rst == 1'b0)
inwaddr <= 4'h0;
else begin
if( fifoaddr == 2'b00 & empty == 1'b1 & inwaddr <= 4'h04)
inwaddr <= inwaddr + 1'b1;
else inwaddr <= 4'h0;
end
end
//inren
always @( posedge rclk or negedge reset )
begin
if (reset == 1'b0 || rst == 1'b0)
inren <= 1'b1;
else begin
if( inwaddr == 4'h04 & inraddr <= 5'h0a )
inren <= 1'b0;
else begin
if( inraddr == 5'h0a )
inren <= 1'b1;
end
end
end
// inwaddr
always @( posedge rclk or negedge reset )
begin
if (reset == 1'b0 || rst == 1'b0)
inwaddr <= 5'h00;
else begin
if( inren <= 1'b0 )
inwaddr <= inraddr +5'h01;
else inwaddr <= 5'h00;
end
end
// fifo_count
always @( posedge rclk or negedge reset )
begin
if (reset == 1'b0 || rst == 1'b0)
fifo_count <= 7'h00;
else begin
if( inren == 1'b0 )
fifo_count <= fifo_count +1'b1;
else fifo_count <= 7'h00;
end
end
//fifo_data
always @( posedge rclk or negedge reset )
begin
if (reset == 1'b0 || rst == 1'b0)
fifodata[fifo_count] <= 8'h00;
else begin
if( inren ==1'b0 )
fifodata[fifo_count] <= data;
end
end
//led_control
always @( posedge wclk or negedge reset)
begin
if(reset == 1'b0 || rst == 1'b0)
begin
led_control <= 1'b0;
lighttime <= 16'h0000;
end
else begin
if( fifodata[0]==proc_data[0] & fifodata[1]==proc_data[1]
& fifodata[2]==proc_data[2] & fifodata[3]==proc_data[3]
& fifodata[4]==proc_data[4] & fifodata[5]==proc_data[5]
& fifodata[6]==proc_data[6] & fifodata[7]==proc_data[7]
& fifodata[8]==proc_data[8] & fifodata[9]==proc_data[9] )
begin
led_control <= 1'b1;
lighttime <= 16'h0000;
end
else if ( led_control == 1'b1 )
begin
if( lighttime == ledtime )
led_control <= 1'b0;
else lighttime <= lighttime + 1'b1;
end
end
end
endmodule
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