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使用VERILOG实现QPSK信号的匹配滤波

# Reading D:/Program/FPGA_software/ModelSim/tcl/vsim/pref.tcl 
# //  ModelSim SE 6.2b Jul 31 2006 
# //
# //  Copyright 2006 Mentor Graphics Corporation
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
# do {test_match_rec.fdo} 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vlog 6.2b Compiler 2006.07 Jul 31 2006
# -- Compiling module match_rec
# 
# Top level modules:
# 	match_rec
# Model Technology ModelSim SE vlog 6.2b Compiler 2006.07 Jul 31 2006
# -- Compiling module test_match_rec
# 
# Top level modules:
# 	test_match_rec
# Model Technology ModelSim SE vlog 6.2b Compiler 2006.07 Jul 31 2006
# -- Compiling module glbl
# 
# Top level modules:
# 	glbl
# vsim -L xilinxcorelib_ver -L unisims_ver -L unimacro_ver -L secureip -lib work -t 1ps test_match_rec glbl 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading work.test_match_rec(fast)
# Loading work.match_rec(fast)
# Loading work.glbl(fast)
# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs.pw.wf
# .main_pane.workspace.interior.cs.nb.canvas.notebook.cs.page2.cs
# .main_pane.signals.interior.cs
run -all
# Break in Module test_match_rec at test_match_rec.v line 63