代码搜索：FPGA加速
找到约 10,000 项符合「FPGA加速」的源代码
代码结果 10,000
www.eeworm.com/read/439407/6932088
v decode_2.v
//
// Module: DECODE_2
// Design: CAM_Top
// Verilog code: RTL / Combinatorial
//
// Synthesis_tool Synopsys FPGA Express ver. 3.2
// Enable Synthesis Option: Verilog Pre-procesor
www.eeworm.com/read/439407/6932101
v decode_3.v
//
// Module: DECODE_3
// Design: CAM_Top
// Verilog code: RTL / Combinatorial
//
// Synthesis_tool Synopsys FPGA Express ver. 3.2
// Enable Synthesis Option: Verilog Pre-procesor
www.eeworm.com/read/439407/6932103
v decode_4.v
//
// Module: DECODE_4
// Design: CAM_Top
// Verilog code: RTL / Combinatorial
//
// Synthesis_tool Synopsys FPGA Express ver. 3.2
// Enable Synthesis Option: Verilog Pre-procesor
www.eeworm.com/read/439407/6932104
v decode_1.v
//
// Module: DECODE_1
// Design: CAM_Top
// Verilog code: RTL / Combinatorial
//
// Synthesis_tool Synopsys FPGA Express ver. 3.2
// Enable Synthesis Option: Verilog Pre-procesor
www.eeworm.com/read/141282/13024839
txt 棋类比赛计时时钟.txt
-- Chess Clock
-- some expressions can not be synthetized,only for Simulation. (such as "AFTER 500 ms")
-- download from: www.fpga.com.cn & www.pld.com.cn
PACKAGE chesspack IS
SUBTYPE hour
www.eeworm.com/read/309739/13665135
xco ram.xco
# BEGIN Project Options
SET flowvendor = Other
SET vhdlsim = True
SET verilogsim = False
SET workingdirectory = D:\Develop\PQS\FPGA\fft_test
SET speedgrade = -4
SET simulationfiles = Behavioral
SET as
www.eeworm.com/read/152843/5665680
c usx2yhwdep.c
/*
* Driver for Tascam US-X2Y USB soundcards
*
* FPGA Loader + ALSA Startup
*
* Copyright (c) 2003 by Karsten Wiese
*
* This program is free software; you can redi
www.eeworm.com/read/135941/5876715
c usx2yhwdep.c
/*
* Driver for Tascam US-X2Y USB soundcards
*
* FPGA Loader + ALSA Startup
*
* Copyright (c) 2003 by Karsten Wiese
*
* This program is free software; you can redi
www.eeworm.com/read/263314/11367772
txt cpu_3rd_package.txt
-- Third Party Package containing functions for Bit_Vector operations
-- download from: www.fpga.com.cn & www.pld.com.cn
-- Cypress Semiconductor WARP 2.0
--
-- Copyright Cypress Semicondu
www.eeworm.com/read/263314/11367803
txt chess_clock.txt
-- Chess Clock
-- some expressions can not be synthetized,only for Simulation. (such as "AFTER 500 ms")
-- download from: www.fpga.com.cn & www.pld.com.cn
PACKAGE chesspack IS
SUBTYPE hour