代码搜索：Encode
找到约 8,258 项符合「Encode」的源代码
代码结果 8,258
www.eeworm.com/read/439407/6932069
vhd encode_4_msb.vhd
--
-- Module: ENCODE_4_MSB
-- Design: CAM_Top
-- VHDL code: RTL / Combinatorial
--
-- Synthesis Synopsys FPGA Express ver. 3.2
-- Use of "pragma synthesis_off/on" and attributes
--
-- Desc
www.eeworm.com/read/439407/6932079
v encode_4_lsb.v
//
// Module: ENCODE_4_LSB
// Design: CAM_Top
// Verilog code: RTL / Combinatorial
//
// Synthesis_tool Synopsys FPGA Express ver. 3.2
// Enable Synthesis Option: Verilog Pre-proceso
www.eeworm.com/read/439407/6932091
v encode_3_msb.v
//
// Module: ENCODE_3_MSB
// Design: CAM_Top
// Verilog code: RTL / Combinatorial
//
// Synthesis_tool Synopsys FPGA Express ver. 3.2
// Enable Synthesis Option: Verilog Pre-proceso
www.eeworm.com/read/439407/6932095
v encode_2_msb.v
//
// Module: ENCODE_2_MSB
// Design: CAM_Top
// Verilog code: RTL / Combinatorial
//
// Synthesis_tool Synopsys FPGA Express ver. 3.2
// Enable Synthesis Option: Verilog Pre-proceso
www.eeworm.com/read/439407/6932097
v encode_4_msb.v
//
// Module: ENCODE_4_MSB
// Design: CAM_Top
// Verilog code: RTL / Combinatorial
//
// Synthesis_tool Synopsys FPGA Express ver. 3.2
// Enable Synthesis Option: Verilog Pre-process
www.eeworm.com/read/439407/6932099
v encode_1_msb.v
//
// Module: ENCODE_1_MSB
// Design: CAM_Top
// Verilog code: RTL / Combinatorial
//
// Synthesis_tool Synopsys FPGA Express ver. 3.2
// Enable Synthesis Option: Verilog Pre-proces
www.eeworm.com/read/461264/7230541
pro fits_ascii_encode.pro
function fits_ascii_encode, sum32
;+
; NAME:
; FITS_ASCII_ENCODE()
; PURPOSE:
; Encode an unsigned longword as an ASCII string to insert in a FITS header
; EXPLANATION:
; Follows the 23 May
www.eeworm.com/read/459617/7270142
java md5encode.java
package com.geminimobile.vacif.socket.util;
import java.security.MessageDigest;
import java.security.NoSuchAlgorithmException;
public class MD5Encode
{
public static String Md5(String plainT
www.eeworm.com/read/457523/7324576
vhd ima_adpcm_encode.vhd
----------------------------------------------------------------------------------
-- Company: VISENGI S.L. (www.visengi.com)
-- Engineer: Victor Lopez Lorenzo (victor.lopez (at) visengi (d
www.eeworm.com/read/454678/7385525
vhd encode2_10.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity encode2_10 is
port (
a: in std_logic_vector ( 15 downto 0);