encode_4_lsb.v

Using Block RAM for High-Performance Read.Write Cams

//
// Module: 	ENCODE_4_LSB
// Design: 	CAM_Top
// Verilog code:	RTL / Combinatorial
//
// Synthesis_tool	Synopsys FPGA Express ver. 3.2 
//		        Enable Synthesis Option: Verilog Pre-procesor
//
// Description: Encode a 16 bits binary address into 4 bits and find if a match occurs
//		if BINARY_ADDR = "0000000000100000" => MATCH_ADDR = "0101" / MATCH_OK = 1 
//		Optional ADDR_VALID = 1 when only one Match (If simultaneous matches can occur)
//		However, the ADDR_VALID generation double the size of the combinatorial logic !
//		if no match found => MATCH_OK = 0 / ADDR_VALID = 0 (MATCH_ADDR is not a valid address)
//		if 2 or more matches found => MATCH_OK = 1 / ADDR_VALID = 0 (MATCH_ADDR is not valid address)
//
// Device: 	VIRTEX Families
//
// Created by: Jean-Louis BRELET / XILINX - VIRTEX Applications
// Converted to Verilog by: Brian Philofsky / Xilinx Design Center
// Date: July 23, 1999
// Version: 1.0
//
// History: 
// 	1. 09/08/99 BP - Converted to Verilog
//
//   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
//                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
//                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
//                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
//
//  Copyright (c) 1999 Xilinx, Inc.  All rights reserved.
//////////////////////////////////////////////////////////////////////////////////////////////////////-

`include "parameters.v"


module ENCODE_4_LSB (BINARY_ADDR,
		     MATCH_ADDR,
`ifdef use_addr_valid
		     ADDR_VALID,
`endif
		     MATCH_OK);

   input [15:0] BINARY_ADDR;

   output [3:0] MATCH_ADDR;  // Match address found
   output 	MATCH_OK;    // '1' if MATCH found

`ifdef use_addr_valid
   output 	ADDR_VALID;  // '1' if MATCH_ADDR is valid (Only one match)
   reg          ADDR_VALID;
`endif

   
   // Signal Declarations:

   reg [3:0] 	MATCH_ADDR;
   
   // wire VCC : std_logic;
   // wire GND : std_logic;

   // assign VCC = 1'b1;
   // assign GND = 1'b0;

   // Convert the binary address in an address bus, ONLY is ONE match is found
   // ADDR_VALID signal generation double the logic size of the encoder !!!

   always @(BINARY_ADDR)
     case (BINARY_ADDR[15:0]) // synopsys parallel_case full_case
       16'b0000000000000001: MATCH_ADDR = 4'b0000;
       16'b0000000000000010: MATCH_ADDR = 4'b0001;
       16'b0000000000000100: MATCH_ADDR = 4'b0010;
       16'b0000000000001000: MATCH_ADDR = 4'b0011;
       16'b0000000000010000: MATCH_ADDR = 4'b0100;
       16'b0000000000100000: MATCH_ADDR = 4'b0101;
       16'b0000000001000000: MATCH_ADDR = 4'b0110;
       16'b0000000010000000: MATCH_ADDR = 4'b0111;
       16'b0000000100000000: MATCH_ADDR = 4'b1000;
       16'b0000001000000000: MATCH_ADDR = 4'b1001;
       16'b0000010000000000: MATCH_ADDR = 4'b1010;
       16'b0000100000000000: MATCH_ADDR = 4'b1011;
       16'b0001000000000000: MATCH_ADDR = 4'b1100;
       16'b0010000000000000: MATCH_ADDR = 4'b1101;
       16'b0100000000000000: MATCH_ADDR = 4'b1110;
       16'b1000000000000000: MATCH_ADDR = 4'b1111;
     endcase // case(BINARY_ADDR[15:0])

`ifdef use_addr_valid
   
   always @(BINARY_ADDR)
     case (BINARY_ADDR[15:0])
       16'b0000000000000000: ADDR_VALID = 1'b0;
       16'b0000000000000001: ADDR_VALID = 1'b0;
       16'b0000000000000010: ADDR_VALID = 1'b0;
       16'b0000000000000100: ADDR_VALID = 1'b0;
       16'b0000000000001000: ADDR_VALID = 1'b0;
       16'b0000000000010000: ADDR_VALID = 1'b0;
       16'b0000000000100000: ADDR_VALID = 1'b0;
       16'b0000000001000000: ADDR_VALID = 1'b0;
       16'b0000000010000000: ADDR_VALID = 1'b0;
       16'b0000000100000000: ADDR_VALID = 1'b0;
       16'b0000001000000000: ADDR_VALID = 1'b0;
       16'b0000010000000000: ADDR_VALID = 1'b0;
       16'b0000100000000000: ADDR_VALID = 1'b0;
       16'b0001000000000000: ADDR_VALID = 1'b0;
       16'b0010000000000000: ADDR_VALID = 1'b0;
       16'b0100000000000000: ADDR_VALID = 1'b0;
       16'b1000000000000000: ADDR_VALID = 1'b0;
       default:              ADDR_VALID = 1'b1;
     endcase // case(BINARY_ADDR[15:0])

`endif // ifdef use_addr_valid
   
   assign MATCH_OK = |BINARY_ADDR;
    

endmodule