encode_1_msb.v

Using Block RAM for High-Performance Read.Write Cams

//
// Module: 	ENCODE_1_MSB
// Design: 	CAM_Top
// Verilog code:	RTL / Combinatorial
//
// Synthesis_tool	Synopsys FPGA Express ver. 3.2 
//	 	        Enable Synthesis Option: Verilog Pre-procesor
//
// Description: Encode a 2 bits binary address into 1 bit, map with the LSB address and find if a match occurs
//		if BINARY_ADDR = "10" => MATCH_ADDR = "1" / MATCH_OK = 1 
//		Optional ADDR_VALID = 1 when only one Match (If simultaneous matches can occur)
//		However, the ADDR_VALID generation double the size of the combinatorial logic !
//		if no match found => MATCH_OK = 0 / ADDR_VALID = 0 (MATCH_ADDR is not a valid address)
//		if 2 or more matches found => MATCH_OK = 1 / ADDR_VALID = 0 (MATCH_ADDR is not valid address)
//
//
// Device: 	VIRTEX Families
//
// Created by: Jean-Louis BRELET / XILINX - VIRTEX Applications
// Converted to Verilog: Brian Philofsky / Xilinx Design Center
// Date: July 23, 1999
// Version: 1.0
//
// History: 
// 	1. 09/08/99 BP - Translated to Verilog
//
//   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
//                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
//                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
//                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
//
//  Copyright (c) 1999 Xilinx, Inc.  All rights reserved.
//////////////////////////////////////////////////////////////////////////////////////////////////////-

`include "parameters.v"


module ENCODE_1_MSB (BINARY_ADDR,
		     ADDR_LSB_0,
		     ADDR_LSB_1,
		     MATCH_ADDR,
`ifdef use_addr_valid 
		     BUS_ADDR_VALID,
		     ADDR_VALID,
`endif
		     MATCH_OK);
   
   input [1:0] BINARY_ADDR;
   input [3:0] ADDR_LSB_0;
   input [3:0] ADDR_LSB_1;

   output [4:0] MATCH_ADDR; // Match address found
   output 	MATCH_OK;   // '1' if MATCH found

`ifdef use_addr_valid
   input [`nb_cam16x8s-1:0] BUS_ADDR_VALID;
   output 	           ADDR_VALID;  // '1' if MATCH_ADDR is valid (Only one match)
   reg 		           ALL_VALID;
`endif
   
   reg [4:0]	MATCH_ADDR;
   
   // Signal Declarations: 
   // wire VCC;
   // wire GND;


   // assign VCC = 1'b1;
   // assign GND = 1'b0;

   // Convert the binary address in an address bus, ONLY is ONE match is found
   // Optional ADDR_VALID signal generation double the logic size of the encoder !!!

   // Begin GATES ONLY implementation //

   always @(BINARY_ADDR or ADDR_LSB_0 or ADDR_LSB_1)
     case (BINARY_ADDR[1:0]) // synopsys parallel_case full_case
       2'b01: MATCH_ADDR[4:0] = {1'b0, ADDR_LSB_0[3:0]};
       2'b10: MATCH_ADDR[4:0] = {1'b1, ADDR_LSB_1[3:0]};
     endcase // case(BINARY_ADDR[1:0])

`ifdef use_addr_valid
   
   always @(BINARY_ADDR)
     case (BINARY_ADDR[1:0])
       2'b01: ALL_VALID = 1'b0;
       2'b10: ALL_VALID = 1'b0;
       default: ALL_VALID = 1'b1;
     endcase // case(BINARY_ADDR[1:0])

   assign 	ADDR_VALID = (~| {BUS_ADDR_VALID, ALL_VALID}) & MATCH_OK;

`endif
   
   // End GATES ONLY implementation //

   // Generate the match signal if one or more matche(s) is/are found

   assign 	MATCH_OK = |BINARY_ADDR;
   

endmodule