encode_2_msb.v

Using Block RAM for High-Performance Read.Write Cams

//
// Module: 	ENCODE_2_MSB
// Design: 	CAM_Top
// Verilog code:	RTL / Combinatorial
//
// Synthesis_tool	Synopsys FPGA Express ver. 3.2 
//		        Enable Synthesis Option: Verilog Pre-procesor
//
// Description: Encode a 4 bits binary address into 2 bits, map with the LSB address and find if a match occurs
//		if BINARY_ADDR = "0010" => MATCH_ADDR = "10" / MATCH_OK = 1 
//		Optional ADDR_VALID = 1 when only one Match (If simultaneous matches can occur)
//		However, the ADDR_VALID generation double the size of the combinatorial logic !
//		if no match found => MATCH_OK = 0 / ADDR_VALID = 0 (MATCH_ADDR is not a valid address)
//		if 2 or more matches found => MATCH_OK = 1 / ADDR_VALID = 0 (MATCH_ADDR is not valid address)
//
//		Choice between GATES ONLY implementation or BUFT implementation. (Select in parameters.v)
//
// Device: 	VIRTEX Families
//
// Created by: Jean-Louis BRELET / XILINX - VIRTEX Applications
// Translated to Verilog by: Brian Philofsky / Xilinx Design Center
// Date: July 23, 1999
// Version: 1.0
//
// History: 
// 	1. 09/09/99 BP - Translated to Verilog
//
//   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
//                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
//                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
//                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
//
//  Copyright (c) 1999 Xilinx, Inc.  All rights reserved.
//////////////////////////////////////////////////////////////////////////////////////////////////////-

`include "parameters.v"


module ENCODE_2_MSB (BINARY_ADDR,
		     ADDR_LSB_0,
		     ADDR_LSB_1,
		     ADDR_LSB_2,
		     ADDR_LSB_3,
		     MATCH_ADDR,
`ifdef use_addr_valid
		     ADDR_VALID,
		     BUS_ADDR_VALID,
`endif
		     MATCH_OK);

   input [3:0] BINARY_ADDR;
   input [3:0] ADDR_LSB_0;
   input [3:0] ADDR_LSB_1;
   input [3:0] ADDR_LSB_2;
   input [3:0] ADDR_LSB_3;

   output [5:0] MATCH_ADDR;
   output 	MATCH_OK;

`ifdef use_addr_valid
   input [`nb_cam16x8s-1:0]	BUS_ADDR_VALID; // Optional
   output 	                ADDR_VALID;
   reg 		                ALL_VALID;
`endif
   
   
   // Signal Declarations:

   

   // wire VCC;
   // wire GND;

   // assign VCC = 1'b1;
   // assign GND = 1'b0;

   // Convert the binary address in an address bus, ONLY is ONE match is found
   // Optional ADDR_VALID signal generation double the logic size of the encoder !!!

   // Choice between gates only implementation or BUFT implementation.

`ifdef use_gates_for_large_muxes
   
   // Begin GATES ONLY implementation //

   reg [5:0] 	MATCH_ADDR;

   always @(BINARY_ADDR or ADDR_LSB_0 or ADDR_LSB_1 or ADDR_LSB_2 or ADDR_LSB_3)
     case (BINARY_ADDR[3:0]) // synopsys full_case parallel_case
       4'b0001: MATCH_ADDR[5:0] = {2'b00, ADDR_LSB_0[3:0]};
       4'b0010: MATCH_ADDR[5:0] = {2'b01, ADDR_LSB_1[3:0]};
       4'b0100: MATCH_ADDR[5:0] = {2'b10, ADDR_LSB_2[3:0]};
       4'b1000: MATCH_ADDR[5:0] = {2'b11, ADDR_LSB_3[3:0]};
     endcase // case(BINARY_ADDR[3:0])
    
   // End GATES ONLY implementation //

`else // !ifdef use_gates_for_large_muxes
   
   // Begin BUFT implementation //
   // 2  statements are used to implement the LSB address in BUFT (mux 4:1) and MSB in gates 
   // (MATCH_ADDR(5 downto 0) <= "xxx" & ADDR_LSB_X);

   wire [5:0] 	MATCH_ADDR;
   reg  [5:4] 	MATCH_ADDR_A;
   wire [3:0] 	MATCH_ADDR_B;

   always @(BINARY_ADDR)
     begin
        case (BINARY_ADDR[3:0]) // synopsys full_case parallel_case
          4'b0001: MATCH_ADDR_A[5:4] = 2'b00;
          4'b0010: MATCH_ADDR_A[5:4] = 2'b01;
          4'b0100: MATCH_ADDR_A[5:4] = 2'b10;
          4'b1000: MATCH_ADDR_A[5:4] = 2'b11;
        endcase // case(BINARY_ADDR)
     end
   
   // Infer Tri-State Buffers Muxes 4:1

   assign MATCH_ADDR_B[3:0] = BINARY_ADDR[0] ? ADDR_LSB_0[3:0] : 4'bzzzz;
   assign MATCH_ADDR_B[3:0] = BINARY_ADDR[1] ? ADDR_LSB_1[3:0] : 4'bzzzz;
   assign MATCH_ADDR_B[3:0] = BINARY_ADDR[2] ? ADDR_LSB_2[3:0] : 4'bzzzz;
   assign MATCH_ADDR_B[3:0] = BINARY_ADDR[3] ? ADDR_LSB_3[3:0] : 4'bzzzz;

   assign MATCH_ADDR = {MATCH_ADDR_A, MATCH_ADDR_B};
   
    // End BUFT implementation //

`endif // !ifdef use_gates_for_large_muxes

`ifdef use_addr_valid
   
   always @(BINARY_ADDR)
     case (BINARY_ADDR[3:0])
       4'b0001: ALL_VALID = 1'b0;
       4'b0010: ALL_VALID = 1'b0;
       4'b0100: ALL_VALID = 1'b0;
       4'b1000: ALL_VALID = 1'b0;
       default: ALL_VALID = 1'b1;
     endcase // case(BINARY_ADDR[3:0])

   assign ADDR_VALID = (~| {BUS_ADDR_VALID, ALL_VALID}) & MATCH_OK;

`endif // ifdef use_addr_valid
   
   
   // Generate the match signal if one or more matche(s) is/are found

   assign MATCH_OK = |BINARY_ADDR;

endmodule // ENCODE_2_MSB