📄 encode_4_msb.v
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//
// Module: ENCODE_4_MSB
// Design: CAM_Top
// Verilog code: RTL / Combinatorial
//
// Synthesis_tool Synopsys FPGA Express ver. 3.2
// Enable Synthesis Option: Verilog Pre-processor
//
// Description: Encode a 16 bits binary address into 4 bits, map with the LSB address and
// find if a match occurs if
// BINARY_ADDR = "0000000000100000" => MATCH_ADDR = "0101" / MATCH_OK = 1
// Optional ADDR_VALID = 1 when only one Match (If simultaneous matches can occur)
// However, the ADDR_VALID generation double the size of the combinatorial logic !
// if no match found => MATCH_OK = 0 / ADDR_VALID = 0 (MATCH_ADDR is not a valid address)
// if 2 or more matches found then
// MATCH_OK = 1 / ADDR_VALID = 0 (MATCH_ADDR is not valid address)
//
// Choice between GATES ONLY implementation or BUFT implementation. (Select in parameters.v)
//
// Device: VIRTEX Families
//
// Created by: Jean-Louis BRELET / XILINX - VIRTEX Applications
// Translated to Verilog by: Brian Philofsky / Xilinx Design Center
// Date: July 23, 1999
// Version: 1.0
//
// History:
// 1. 09/09/99 BP - Translated to Verilog
//
// Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
// WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY
// IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
// A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
//
// Copyright (c) 1999 Xilinx, Inc. All rights reserved.
//////////////////////////////////////////////////////////////////////////////////////////////////////-
`include "parameters.v"
module ENCODE_4_MSB (BINARY_ADDR,
ADDR_LSB_0,
ADDR_LSB_1,
ADDR_LSB_2,
ADDR_LSB_3,
ADDR_LSB_4,
ADDR_LSB_5,
ADDR_LSB_6,
ADDR_LSB_7,
ADDR_LSB_8,
ADDR_LSB_9,
ADDR_LSB_10,
ADDR_LSB_11,
ADDR_LSB_12,
ADDR_LSB_13,
ADDR_LSB_14,
ADDR_LSB_15,
MATCH_ADDR,
`ifdef use_addr_valid
ADDR_VALID,
BUS_ADDR_VALID,
`endif
MATCH_OK);
input [15:0] BINARY_ADDR;
input [3:0] ADDR_LSB_0;
input [3:0] ADDR_LSB_1;
input [3:0] ADDR_LSB_2;
input [3:0] ADDR_LSB_3;
input [3:0] ADDR_LSB_4;
input [3:0] ADDR_LSB_5;
input [3:0] ADDR_LSB_6;
input [3:0] ADDR_LSB_7;
input [3:0] ADDR_LSB_8;
input [3:0] ADDR_LSB_9;
input [3:0] ADDR_LSB_10;
input [3:0] ADDR_LSB_11;
input [3:0] ADDR_LSB_12;
input [3:0] ADDR_LSB_13;
input [3:0] ADDR_LSB_14;
input [3:0] ADDR_LSB_15;
output [7:0] MATCH_ADDR; // Match address found
output MATCH_OK; // '1' if MATCH found
`ifdef use_addr_valid
input [`nb_cam16x8s-1:0] BUS_ADDR_VALID; // Optional
output ADDR_VALID; // '1' if MATCH_ADDR is valid (Only one match)
reg ALL_VALID;
`endif
// Signal Declarations:
// wire VCC;
// wire GND;
// assign VCC = 1'b1;
// assign GND = 1'b0;
// Convert the binary address in an address bus, ONLY is ONE match is found
// Optional ADDR_VALID signal generation double the logic size of the encoder !!!
// Choice between gates only implementation or BUFT implementation.
`ifdef use_gates_for_large_muxes
// Begin GATES ONLY implementation //
reg [7:0] MATCH_ADDR;
always @(BINARY_ADDR or ADDR_LSB_0 or ADDR_LSB_1 or ADDR_LSB_2 or ADDR_LSB_3 or
ADDR_LSB_4 or ADDR_LSB_5 or ADDR_LSB_6 or ADDR_LSB_7 or
ADDR_LSB_8 or ADDR_LSB_9 or ADDR_LSB_10 or ADDR_LSB_11 or
ADDR_LSB_12 or ADDR_LSB_13 or ADDR_LSB_14 or ADDR_LSB_15)
case (BINARY_ADDR[15:0]) // synopsys parallel_case full_case
16'b0000000000000001: MATCH_ADDR[7:0] = {4'b0000, ADDR_LSB_0[3:0]};
16'b0000000000000010: MATCH_ADDR[7:0] = {4'b0001, ADDR_LSB_1[3:0]};
16'b0000000000000100: MATCH_ADDR[7:0] = {4'b0010, ADDR_LSB_2[3:0]};
16'b0000000000001000: MATCH_ADDR[7:0] = {4'b0011, ADDR_LSB_3[3:0]};
16'b0000000000010000: MATCH_ADDR[7:0] = {4'b0100, ADDR_LSB_4[3:0]};
16'b0000000000100000: MATCH_ADDR[7:0] = {4'b0101, ADDR_LSB_5[3:0]};
16'b0000000001000000: MATCH_ADDR[7:0] = {4'b0110, ADDR_LSB_6[3:0]};
16'b0000000010000000: MATCH_ADDR[7:0] = {4'b0111, ADDR_LSB_7[3:0]};
16'b0000000100000000: MATCH_ADDR[7:0] = {4'b1000, ADDR_LSB_8[3:0]};
16'b0000001000000000: MATCH_ADDR[7:0] = {4'b1001, ADDR_LSB_9[3:0]};
16'b0000010000000000: MATCH_ADDR[7:0] = {4'b1010, ADDR_LSB_10[3:0]};
16'b0000100000000000: MATCH_ADDR[7:0] = {4'b1011, ADDR_LSB_11[3:0]};
16'b0001000000000000: MATCH_ADDR[7:0] = {4'b1100, ADDR_LSB_12[3:0]};
16'b0010000000000000: MATCH_ADDR[7:0] = {4'b1101, ADDR_LSB_13[3:0]};
16'b0100000000000000: MATCH_ADDR[7:0] = {4'b1110, ADDR_LSB_14[3:0]};
16'b1000000000000000: MATCH_ADDR[7:0] = {4'b1111, ADDR_LSB_15[3:0]};
endcase // case(BINARY_ADDR[15:0])
// End GATES ONLY implementation //
`else // !ifdef use_gates_for_large_muxes
// Begin BUFT implementation //
// 2 statements are used to implement the LSB address in BUFT (mux 16:1) and MSB in gates
// (MATCH_ADDR(7 downto 0) <= "xxxx" & ADDR_LSB_X);
wire [7:0] MATCH_ADDR;
reg [7:4] MATCH_ADDR_A;
wire [3:0] MATCH_ADDR_B;
always @(BINARY_ADDR)
begin
case (BINARY_ADDR[15:0]) // synopsys parallel_case full_case
16'b0000000000000001: MATCH_ADDR_A[7:4] = 4'b0000;
16'b0000000000000010: MATCH_ADDR_A[7:4] = 4'b0001;
16'b0000000000000100: MATCH_ADDR_A[7:4] = 4'b0010;
16'b0000000000001000: MATCH_ADDR_A[7:4] = 4'b0011;
16'b0000000000010000: MATCH_ADDR_A[7:4] = 4'b0100;
16'b0000000000100000: MATCH_ADDR_A[7:4] = 4'b0101;
16'b0000000001000000: MATCH_ADDR_A[7:4] = 4'b0110;
16'b0000000010000000: MATCH_ADDR_A[7:4] = 4'b0111;
16'b0000000100000000: MATCH_ADDR_A[7:4] = 4'b1000;
16'b0000001000000000: MATCH_ADDR_A[7:4] = 4'b1001;
16'b0000010000000000: MATCH_ADDR_A[7:4] = 4'b1010;
16'b0000100000000000: MATCH_ADDR_A[7:4] = 4'b1011;
16'b0001000000000000: MATCH_ADDR_A[7:4] = 4'b1100;
16'b0010000000000000: MATCH_ADDR_A[7:4] = 4'b1101;
16'b0100000000000000: MATCH_ADDR_A[7:4] = 4'b1110;
16'b1000000000000000: MATCH_ADDR_A[7:4] = 4'b1111;
endcase // case(BINARY_ADDR)
end // always @ (BINARY_ADDR)
// Infer Tri-State Buffers Muxes 16:1
assign MATCH_ADDR_B = BINARY_ADDR[0] ? ADDR_LSB_0[3:0] : 4'bzzzz;
assign MATCH_ADDR_B = BINARY_ADDR[1] ? ADDR_LSB_1[3:0] : 4'bzzzz;
assign MATCH_ADDR_B = BINARY_ADDR[2] ? ADDR_LSB_2[3:0] : 4'bzzzz;
assign MATCH_ADDR_B = BINARY_ADDR[3] ? ADDR_LSB_3[3:0] : 4'bzzzz;
assign MATCH_ADDR_B = BINARY_ADDR[4] ? ADDR_LSB_4[3:0] : 4'bzzzz;
assign MATCH_ADDR_B = BINARY_ADDR[5] ? ADDR_LSB_5[3:0] : 4'bzzzz;
assign MATCH_ADDR_B = BINARY_ADDR[6] ? ADDR_LSB_6[3:0] : 4'bzzzz;
assign MATCH_ADDR_B = BINARY_ADDR[7] ? ADDR_LSB_7[3:0] : 4'bzzzz;
assign MATCH_ADDR_B = BINARY_ADDR[8] ? ADDR_LSB_8[3:0] : 4'bzzzz;
assign MATCH_ADDR_B = BINARY_ADDR[9] ? ADDR_LSB_9[3:0] : 4'bzzzz;
assign MATCH_ADDR_B = BINARY_ADDR[10] ? ADDR_LSB_10[3:0] : 4'bzzzz;
assign MATCH_ADDR_B = BINARY_ADDR[11] ? ADDR_LSB_11[3:0] : 4'bzzzz;
assign MATCH_ADDR_B = BINARY_ADDR[12] ? ADDR_LSB_12[3:0] : 4'bzzzz;
assign MATCH_ADDR_B = BINARY_ADDR[13] ? ADDR_LSB_13[3:0] : 4'bzzzz;
assign MATCH_ADDR_B = BINARY_ADDR[14] ? ADDR_LSB_14[3:0] : 4'bzzzz;
assign MATCH_ADDR_B = BINARY_ADDR[15] ? ADDR_LSB_15[3:0] : 4'bzzzz;
assign MATCH_ADDR = {MATCH_ADDR_A, MATCH_ADDR_B};
// End BUFT implementation //
`endif // !ifdef use_gates_for_large_muxes
`ifdef use_addr_valid
always @(BINARY_ADDR)
case (BINARY_ADDR[15:0])
16'b0000000000000001: ALL_VALID = 1'b0;
16'b0000000000000010: ALL_VALID = 1'b0;
16'b0000000000000100: ALL_VALID = 1'b0;
16'b0000000000001000: ALL_VALID = 1'b0;
16'b0000000000010000: ALL_VALID = 1'b0;
16'b0000000000100000: ALL_VALID = 1'b0;
16'b0000000001000000: ALL_VALID = 1'b0;
16'b0000000010000000: ALL_VALID = 1'b0;
16'b0000000100000000: ALL_VALID = 1'b0;
16'b0000001000000000: ALL_VALID = 1'b0;
16'b0000010000000000: ALL_VALID = 1'b0;
16'b0000100000000000: ALL_VALID = 1'b0;
16'b0001000000000000: ALL_VALID = 1'b0;
16'b0010000000000000: ALL_VALID = 1'b0;
16'b0100000000000000: ALL_VALID = 1'b0;
16'b1000000000000000: ALL_VALID = 1'b0;
default: ALL_VALID = 1'b1;
endcase // case(BINARY_ADDR[15:0])
assign ADDR_VALID = (~| {BUS_ADDR_VALID, ALL_VALID}) & MATCH_OK;
`endif // ifdef use_addr_valid
// Generate the match signal if one or more matche(s) is/are found
assign MATCH_OK = |BINARY_ADDR;
endmodule // ENCODE_4_MSB
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