代码搜索：Clocking
找到约 219 项符合「Clocking」的源代码
代码结果 219
www.eeworm.com/read/345352/3200339
v pl4_lite_snk_clk.v
/******************************************************************************
// PL4 Clocking Scheme -- Verilog RTL Design
*************************************************************************
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v pl4_lite_src_clk.v
/******************************************************************************
// PL4 Clocking Scheme -- Verilog RTL Design
*************************************************************************
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h internal.h
#ifndef __INTERNAL_H__
#define __INTERNAL_H__
#ifdef __cplusplus
extern "C" {
#endif
// F/W code version
// !!!! Don't allow modification !!!
#define SW_VERSION 239
#define SW_
www.eeworm.com/read/17663/752004
lfp correlate_and_accumulate_xst.lfp
# begin LFP file C:\training\desperf\labs\clocking\verilog\clocking_lab\correlate_and_accumulate_xst.lfp
designfile correlate_and_accumulate.v
parttype xc4vlx15-12-sf363
bus_delimiter 2;
set_busde
www.eeworm.com/read/418844/2082765
lfp correlate_and_accumulate_xst.lfp
# begin LFP file C:\training\desperf\labs\clocking\verilog\clocking_lab\correlate_and_accumulate_xst.lfp
designfile correlate_and_accumulate.v
parttype xc4vlx15-12-sf363
bus_delimiter 2;
set_busde
www.eeworm.com/read/403299/2313112
v arb_if.v
interface arb_if(input bit clk);
// LAB: Add signal definitions
// LAB: Add Clocking block for synchronous signals
endinterface
www.eeworm.com/read/231864/14217307
i c240_cfg.i
;=============================================================================
; F240 Clocking configuration file for the Flash utility.
;
; Filename : C240_CFG.I
; Date : 26 Feb 97
; Revision :
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i c240_cfg.i
;=============================================================================
; F240 Clocking configuration file for the Flash utility.
;
; Filename : C240_CFG.I
; Date : 26 Feb 97
; Revision :
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ucf qdr2_test.ucf
#######################################################################
# XILINX QDR SRAM Local clocking Virtex-II Pro interface
# APD APPS 2004
# Custom constraints file - version 1 DDR400
#
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ucf qdr2_test.ucf
#######################################################################
# XILINX QDR SRAM Local clocking Virtex-II Pro interface
# APD APPS 2004
# Custom constraints file - version 1 DDR400
#