pl4_lite_src_clk.v

spi接口的vhdl实现

/******************************************************************************
// PL4 Clocking Scheme -- Verilog RTL Design
*******************************************************************************/


/******************************************************************************
*
* This file is owned and controlled by Xilinx and must be used solely
* for design, simulation, implementation and creation of design files
* limited to Xilinx devices or technologies. Use with non/Xilinx
* devices or technologies is expressly prohibited and immediately
* terminates your license.
*
* Xilinx products are not intended for use in life support
* appliances, devices, or systems. Use in such applications is
* expressly prohibited.
*
*            **************************************
*            ** Copyright (C) 2003, Xilinx, Inc. **
*            ** All Rights Reserved.             **
*            **************************************
*
*******************************************************************************
* Filename: pl4_lite_src_clk.v
*
* Description:
*  This module implements clocking scheme for the slave clock, using a DCM.
*  The CLK0 is locally inverted
*
******************************************************************************/
`timescale 1ps/1ps


/******************************************************************************
* Module Declaration
*******************************************************************************/
module pl4_lite_src_clk(
  // Source Clock Signal Inputs
  SysClk_P,
  SysClk_N,
  DcmReset_SysClk,

  // Source Clock Signal Outputs
  Locked_SysClk,
  SysClk0_buf,
  SysClk180_buf,

  // Status Clock Signal Inputs
  // PL4 source status inputs in LVDS
  TSClk_P,
  TSClk_N,

  // Status Clock Signal Outputs
  DcmLost_SysClk,
  SrcClksRdy,
  TSClk_buf
  );

/******************************************************************************
* Port Declarations
*******************************************************************************/
  //Source Clock Signal Inputs
  input     SysClk_P;
  input     SysClk_N;
  input     DcmReset_SysClk;

  // Source Clock Signal Outputs
  output    Locked_SysClk;
  output    SysClk0_buf;
  output    SysClk180_buf;

  // Status Clock Signal Inputs
  input     TSClk_P;
  input     TSClk_N;


  // Status Clock Signal Outputs
  output    DcmLost_SysClk;
  output    SrcClksRdy;
  output    TSClk_buf;

/*******************************************************************************
* Definition of Ports
********************************************************************************
*  Source Clock Signal Inputs
*    SysClk_P          : External differential reference clock
*    SysClk_N          : External differential reference clock
*    DcmReset_SysClk   : SysClk DCM Reset signal
*
*  Source Clock Signal Outputs
*    Locked_SysClk     : SysClk DCM locked signal
*    SysClk0_buf       : SysClk Clk0 Output
*    SysClk180_buf     : SysClk Clk180 Output
*
*  Status Clock Signal Inputs
*    TSClk             : PL4 input Status Clock
*
*  Status Clock Signal Outputs
*    DcmLost_SysClk    : Indicates the SysClk DCM lost the input clock
*    SrcClksRdy        : Indicates all clocks are locked and ready for use
*    TSClk_buf         : Internal Status Clock: Calendar and Status logic
*******************************************************************************/



/******************************************************************************
* Wire Declarations for internal signals
*******************************************************************************/
  wire SysClk_int;
  wire SysClk0_dcm;
  wire SysClk180_dcm;
  wire SrcClk_dcmo;
  wire Locked_SrcClk_dcmo;
  wire [7:0] TDSTATUS_int;

  wire TSClk_i;
  wire TSClk_rdy;
  wire TSClk_bufg_i;

  reg  SrcClksRdy_i;

  wire GND;
  wire VCC;

/******************************************************************************
* Constant Declaration
*******************************************************************************/

// Connect PORTS to signals
  assign GND            = 0;
  assign VCC            = 1;
  assign Locked_SysClk  = Locked_SrcClk_dcmo;
  assign SysClk0_buf    = SysClk0_dcm;
  assign SysClk180_buf  = SysClk180_dcm;
  assign DcmLost_SysClk = TDSTATUS_int[1];

  assign TSClk_buf     = TSClk_bufg_i;

/******************************************************************************
* SysClk Clocking section
*******************************************************************************/

/******************************************************************************
* Differential Clock Input Buffer Instantiation
*    1.) Inputs differential SysClk clock signal
*    2.) Drives internal BUFG in turn feeding DLL ClkIn
*******************************************************************************/
  IBUFGDS sysclk_ibufg0 (
    .I  (SysClk_P),
    .IB (SysClk_N),
    .O  (SysClk_int)
    );

/******************************************************************************
* tdclk_bufg BUFG Instantiation:
*    1.) Takes clock input from differential input buffer
*    2.) Feeds the DCM Clock Input
*    3.) Drives SysClk0_buf output signal
*******************************************************************************/
  BUFG tdclk_bufg0 (
    .I  (SrcClk_dcmo),
    .O  (SysClk0_dcm)
    );

/******************************************************************************
* SysClk180_buf INVERSION Instantiation:
*    1.) Takes output SysClk0_dcm
*    2.) Inverts the clock to create SysClk180 output signal
*******************************************************************************/
  INV sysclk_inv0 (
    .I  (SysClk0_dcm),
    .O  (SysClk180_dcm)
    );

/*****************************************************************************/


/******************************************************************************
*  TDClk DCM Instantiation
*    CLkIn: 400 MHz SysClk
*    ClkFB: 200 MHz (ClkIn div 2)
*    Clk0:  200 MHz (ClkIn div 2)
*******************************************************************************/
  DCM tdclk_dcm0 (
    .CLKIN    (SysClk_int),
    .CLKFB    (SysClk0_dcm),
    .DSSEN    (GND),
    .PSINCDEC (GND),
    .PSEN     (GND),
    .PSCLK    (GND),
    .RST      (DcmReset_SysClk),
    .CLK0     (SrcClk_dcmo),
    .CLK90    (),
    .CLK180   (),
    .CLK270   (),
    .CLK2X    (),
    .CLK2X180 (),
    .CLKDV    (),
    .CLKFX    (),
    .CLKFX180 (),
    .LOCKED   (Locked_SrcClk_dcmo),
    .PSDONE   (),
    .STATUS   (TDSTATUS_int)
     );

// XST Synthesis Attributes
// synthesis attribute CLK_FEEDBACK of tdclk_dcm0 is "1X"
// synthesis attribute CLKIN_DIVIDE_BY_2 of tdclk_dcm0 is "FALSE"
// synthesis attribute DLL_FREQUENCY_MODE of tdclk_dcm0 is "LOW"

// synthesis translate_off
    defparam tdclk_dcm0.CLK_FEEDBACK        ="1X";
    defparam tdclk_dcm0.CLKIN_DIVIDE_BY_2   ="FALSE";
    defparam tdclk_dcm0.DLL_FREQUENCY_MODE  ="LOW";
// synthesis translate_on


//****************************************************************************
// TStat
//****************************************************************************

//****************************************************************************
// Instantiate LVDS IBUF for the TStat  and TSClk pins
//****************************************************************************
  IBUFGDS  tsclk_ibufg0(
    .I  (TSClk_P),
    .IB (TSClk_N),
    .O  (TSClk_i)
   );


//****************************************************************************
// Instantiate BUFG for the TSClk pins
//****************************************************************************
  BUFG tsclk_bufg0 (
    .I  (TSClk_i),
    .O  (TSClk_bufg_i)
    );


/******************************************************************************
* Instantiate the TSClk_rdy FDR
******************************************************************************/
  FDR tsclk_rdy0 (
    .D  (1'b1),
    .C  (TSClk_bufg_i),
    .R  (1'b0),
    .Q  (TSClk_rdy)
    );

/*****************************************************************************/


/******************************************************************************
* Create SrcClksRdy
******************************************************************************/
 initial
  begin
   SrcClksRdy_i <= 1'b0;
  end

 always @(posedge SysClk0_dcm)
  begin
   SrcClksRdy_i <= TSClk_rdy & Locked_SrcClk_dcmo;
  end




 assign SrcClksRdy = SrcClksRdy_i;


endmodule