pl4_lite_snk_clk.v

spi接口的vhdl实现

/******************************************************************************
// PL4 Clocking Scheme -- Verilog RTL Design
*******************************************************************************/


/******************************************************************************
*
* This file is owned and controlled by Xilinx and must be used solely
* for design, simulation, implementation and creation of design files
* limited to Xilinx devices or technologies. Use with non/Xilinx
* devices or technologies is expressly prohibited and immediately
* terminates your license.
*
* Xilinx products are not intended for use in life support
* appliances, devices, or systems. Use in such applications is
* expressly prohibited.
*
*            **************************************
*            ** Copyright (C) 2003, Xilinx, Inc. **
*            ** All Rights Reserved.             **
*            **************************************
*
******************************************************************************/
`timescale 1ps/1ps


/******************************************************************************
* Module Declaration
*******************************************************************************/
module pl4_lite_snk_clk(
  // Sink Clock Signal Inputs
  RDClk_P,
  RDClk_N,
  DcmReset_RDClk,

  // Sink Clock Signal Outputs
  Locked_RDClk,
  DcmLost_RDClk,
  RDClk0_user,
  RDClk180_user
  );

/******************************************************************************
* Port Declarations
*******************************************************************************/
  //Sink Clock Signal Inputs
  input     RDClk_P;
  input     RDClk_N;
  input     DcmReset_RDClk;

  // Sink Clock Signal Outputs
  output    Locked_RDClk;
  output    DcmLost_RDClk;
  output    RDClk0_user;
  output    RDClk180_user;

/*******************************************************************************
* Definition of Ports
********************************************************************************
*  Sink Clock Signal Inputs
*    RDClk_P          : External differential reference clock
*    RDClk_N          : External differential reference clock
*    DcmReset_RDClk   : RDClk DCM Reset signal
*
*  Sink Clock Signal Outputs
*    Locked_RDClk     : RDClk DCM locked signal
*    DcmLost_RDClk    : RDClk DCM lost the input clock
*    RDClk0_user      : RDClk DCM Clk0 Output
*    RDClk180_user    : RDClk DCM Clk180 Output
*******************************************************************************/



/******************************************************************************
* Wire Declarations for internal signals
*******************************************************************************/
  wire RDClk_int;
  wire RDClk0_dcm;
  wire SnkClk_dcmo;
  wire Locked_RDClk_dcmo;
  wire [7:0] RDSTATUS_int;
  wire GND;


/******************************************************************************
* Ground Assignement for empty DLL Connections
*******************************************************************************/
  assign GND           = 0;

/******************************************************************************
* Differential Clock Input Buffer Instantiation
*    1.) Inputs differential RDClk clock signal
*    2.) Drives internal BUFG in turn feeding DLL ClkIn
*******************************************************************************/
  IBUFGDS rdclk_ibufg0 (
    .I  (RDClk_P),
    .IB (RDClk_N),
    .O  (RDClk_int)
    );

/******************************************************************************
* tdclk0_bufg BUFG Instantiation:
*    1.) Takes clock input from differential input buffer
*    2.) Feeds the DCM Clock Input
*    3.) Drives RDClk0_bufg output signal
*******************************************************************************/
  BUFG rdclk_bufg0 (
    .I  (SnkClk_dcmo),
    .O  (RDClk0_dcm)
    );

/******************************************************************************
*  RDClk DCM Instantiation
*    CLkIn: 400 MHz RDClk
*    ClkFB: 200 MHz (ClkIn div 2)
*    Clk0:  200 MHz (ClkIn div 2)
*******************************************************************************/
  DCM rdclk_dcm0 (
    .CLKIN    (RDClk_int),
    .CLKFB    (RDClk0_dcm),
    .DSSEN    (GND),
    .PSINCDEC (GND),
    .PSEN     (GND),
    .PSCLK    (GND),
    .RST      (DcmReset_RDClk),
    .CLK0     (SnkClk_dcmo),
    .CLK90    (),
    .CLK180   (),
    .CLK270   (),
    .CLK2X    (),
    .CLK2X180 (),
    .CLKDV    (),
    .CLKFX    (),
    .CLKFX180 (),
    .LOCKED   (Locked_RDClk_dcmo),
    .PSDONE   (),
    .STATUS   (RDSTATUS_int)
     );

// XST Synthesis Attributes
// synthesis attribute CLK_FEEDBACK of rdclk_dcm0 is "1X"
// synthesis attribute DLL_FREQUENCY_MODE  of rdclk_dcm0 is "LOW"
// synthesis attribute CLKOUT_PHASE_SHIFT  of rdclk_dcm0 is "FIXED"
// synthesis attribute PHASE_SHIFT         of rdclk_dcm0 is "62"
// synthesis attribute DESKEW_ADJUST       of rdclk_dcm0 is "SOURCE_SYNCHRONOUS"

// synthesis translate_off
    defparam rdclk_dcm0.CLK_FEEDBACK        ="1X";
    defparam rdclk_dcm0.DLL_FREQUENCY_MODE  ="LOW";
    defparam rdclk_dcm0.CLKOUT_PHASE_SHIFT  ="FIXED";
    defparam rdclk_dcm0.PHASE_SHIFT         = 62;
    defparam rdclk_dcm0.DESKEW_ADJUST       ="SOURCE_SYNCHRONOUS";
// synthesis translate_on

/******************************************************************************
// Connect PORTS to signals
******************************************************************************/
  assign Locked_RDClk  = Locked_RDClk_dcmo;
  assign RDClk0_user   = RDClk0_dcm;
  assign RDClk180_user = ~RDClk0_dcm;
  assign DcmLost_RDClk = RDSTATUS_int[1];

endmodule