qdr2_test.ucf

XILINX memory interface generator. XILINX的外部存储器接口。

#######################################################################
#  XILINX QDR SRAM Local clocking Virtex-II Pro interface
#  APD APPS 2004
#  Custom constraints file - version 1 DDR400 
#  Constraints for reference design and ML365 board only
#######################################################################

############################################################################
# Clock constraints ML 365 Location contraints / QDR B
############################################################################
                                                                            
NET "QDR_Interface_clocks/CLK_BUF" TNM_NET = FFS(*) "SYS_CLK";                              
TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK" 5.0 ns HIGH 50 %;                  

INST "CLK200" 	   	LOC = AJ17; 	   #On board oscillator 200 MHz
INST "CLK200N" 		LOC = AH17; 	   #On board oscillator 200MHz


INST "Reset" 		LOC = AE21;       
INST "Result_Reg" 	LOC = AE15; #use LED D11

# JP HEADERS PINS
#INST "UDV" 			LOC = AL12; 
#INST "RCtrl" 		LOC = AD16;
#INST "WCtrl" 		LOC = AE16;
#INST "DCM_LCK" 		LOC = AM14;
#INST "D0_capture" 	LOC = AM13;
#INST "D0_FIFO" 		LOC = AF16;
#INST "D0_Reference"	LOC = AG16;
#INST "CLOCK_TEST" 	LOC = AF17;

## 
#INST "A_R" LOC = AF32;
#INST "A_W" LOC = AF31; 
#INST "C_R" LOC = H10;
#INST "C_W" LOC = J10;
#INST "U28" LOC = U28;
#INST "H26" LOC = H26;
      
                                                                        
############################################################################
# Synchronous CE constraints                                               #
############################################################################
                                                                        
INST "QDR_Interface_B/Read_data_path/FD_R_n_0" LOC = SLICE_X88Y92;
INST "QDR_Interface_B/Read_data_path/FD_R_n_0_DC" LOC = SLICE_X88Y80;
INST "QDR_Interface_B/Read_data_path/FD_R_n_2_DC" LOC = SLICE_X88Y80;
INST "QDR_Interface_B/Read_data_path/FD_R_n_1_DC" LOC = SLICE_X91Y81;   
INST "QDR_Interface_B/Read_data_path/FD_R_n_3_DC" LOC = SLICE_X91Y81;

NET "QDR_Interface_B/R_n_recapture" MAXDELAY = 800ps; 

NET "QDR_Interface_B/Read_data_path/CE_R_FB0" MAXDELAY = 1000ps; 
NET "QDR_Interface_B/Read_data_path/CE_R_FB1" MAXDELAY = 1000ps;
NET "QDR_Interface_B/Read_data_path/CE_R_FB2" MAXDELAY = 1000ps;
NET "QDR_Interface_B/Read_data_path/CE_R_FB3" MAXDELAY = 1000ps;
  
######################################################################################################
# DCM Location Constraints
######################################################################################################

INST "QDR_Interface_clocks/INST_DCM_TOMEMORY" LOC="DCM_X3Y0";

######################################################################################################
# Calibration Circuit Constraints
######################################################################################################

INST "QDR_Interface_B/cal_inst/cal_dcm" LOC="DCM_X2Y0";

NET "QDR_Interface_B/cal_inst/ckt_to_cal/delay1" KEEP;
NET "QDR_Interface_B/cal_inst/ckt_to_cal/delay2" KEEP;
NET "QDR_Interface_B/cal_inst/ckt_to_cal/delay3" KEEP;
NET "QDR_Interface_B/cal_inst/ckt_to_cal/delay4" KEEP;
NET "QDR_Interface_B/cal_inst/ckt_to_cal/delay5" KEEP;

NET "QDR_Interface_B/cal_inst/ckt_to_cal/delay1" S;
NET "QDR_Interface_B/cal_inst/ckt_to_cal/delay2" S;
NET "QDR_Interface_B/cal_inst/ckt_to_cal/delay3" S;
NET "QDR_Interface_B/cal_inst/ckt_to_cal/delay4" S;
NET "QDR_Interface_B/cal_inst/ckt_to_cal/delay5" S;

NET "QDR_Interface_B/cal_inst/cal_ctl0/selTap(0)" S;
NET "QDR_Interface_B/cal_inst/cal_ctl0/selTap(1)" S;
NET "QDR_Interface_B/cal_inst/cal_ctl0/selTap(2)" S;
NET "QDR_Interface_B/cal_inst/cal_ctl0/selTap(3)" S;
NET "QDR_Interface_B/cal_inst/cal_ctl0/selTap(4)" S;

NET "QDR_Interface_B/cal_inst/cal_ctl0/selTap(0)" KEEP;
NET "QDR_Interface_B/cal_inst/cal_ctl0/selTap(1)" KEEP;
NET "QDR_Interface_B/cal_inst/cal_ctl0/selTap(2)" KEEP;
NET "QDR_Interface_B/cal_inst/cal_ctl0/selTap(3)" KEEP;
NET "QDR_Interface_B/cal_inst/cal_ctl0/selTap(4)" KEEP;

NET "QDR_Interface_B/Read_data_path/cq_delay0_col0/delay1" KEEP;
NET "QDR_Interface_B/Read_data_path/cq_delay0_col0/delay2" KEEP;
NET "QDR_Interface_B/Read_data_path/cq_delay0_col0/delay3" KEEP;     
NET "QDR_Interface_B/Read_data_path/cq_delay0_col0/delay4" KEEP;     
NET "QDR_Interface_B/Read_data_path/cq_delay0_col0/delay5" KEEP;     

NET "QDR_Interface_B/Read_data_path/cq_delay0_col0/delay1" S;
NET "QDR_Interface_B/Read_data_path/cq_delay0_col0/delay2" S;      
NET "QDR_Interface_B/Read_data_path/cq_delay0_col0/delay3" S;
NET "QDR_Interface_B/Read_data_path/cq_delay0_col0/delay4" S;            
NET "QDR_Interface_B/Read_data_path/cq_delay0_col0/delay5" S;

NET "QDR_Interface_B/Read_data_path/cq_delay0_col1/delay1" KEEP;
NET "QDR_Interface_B/Read_data_path/cq_delay0_col1/delay2" KEEP;
NET "QDR_Interface_B/Read_data_path/cq_delay0_col1/delay3" KEEP;             
NET "QDR_Interface_B/Read_data_path/cq_delay0_col1/delay4" KEEP;       
NET "QDR_Interface_B/Read_data_path/cq_delay0_col1/delay5" KEEP;              

NET "QDR_Interface_B/Read_data_path/cq_delay0_col1/delay1" S;
NET "QDR_Interface_B/Read_data_path/cq_delay0_col1/delay2" S;
NET "QDR_Interface_B/Read_data_path/cq_delay0_col1/delay3" S;
NET "QDR_Interface_B/Read_data_path/cq_delay0_col1/delay4" S;
NET "QDR_Interface_B/Read_data_path/cq_delay0_col1/delay5" S;

NET "QDR_Interface_B/Read_data_path/cq_delay1_col0/delay1" KEEP;
NET "QDR_Interface_B/Read_data_path/cq_delay1_col0/delay2" KEEP;
NET "QDR_Interface_B/Read_data_path/cq_delay1_col0/delay3" KEEP;
NET "QDR_Interface_B/Read_data_path/cq_delay1_col0/delay4" KEEP;
NET "QDR_Interface_B/Read_data_path/cq_delay1_col0/delay5" KEEP;

NET "QDR_Interface_B/Read_data_path/cq_delay1_col0/delay1" S;
NET "QDR_Interface_B/Read_data_path/cq_delay1_col0/delay2" S;
NET "QDR_Interface_B/Read_data_path/cq_delay1_col0/delay3" S;
NET "QDR_Interface_B/Read_data_path/cq_delay1_col0/delay4" S;
NET "QDR_Interface_B/Read_data_path/cq_delay1_col0/delay5" S;

NET "QDR_Interface_B/Read_data_path/cq_delay1_col1/delay1" KEEP;
NET "QDR_Interface_B/Read_data_path/cq_delay1_col1/delay2" KEEP;
NET "QDR_Interface_B/Read_data_path/cq_delay1_col1/delay3" KEEP;
NET "QDR_Interface_B/Read_data_path/cq_delay1_col1/delay4" KEEP;
NET "QDR_Interface_B/Read_data_path/cq_delay1_col1/delay5" KEEP;

NET "QDR_Interface_B/Read_data_path/cq_delay1_col1/delay1" S;
NET "QDR_Interface_B/Read_data_path/cq_delay1_col1/delay2" S;
NET "QDR_Interface_B/Read_data_path/cq_delay1_col1/delay3" S;
NET "QDR_Interface_B/Read_data_path/cq_delay1_col1/delay4" S;
NET "QDR_Interface_B/Read_data_path/cq_delay1_col1/delay5" S;

INST "QDR_Interface_B/cal_inst" AREA_GROUP=gp1;
AREA_GROUP "gp1" RANGE = SLICE_X52Y0:SLICE_X75Y11;

INST "QDR_Interface_B/cal_inst/cal_clkd2" LOC = SLICE_X72Y0;
INST "QDR_Interface_B/cal_inst/cal_phClkd2" LOC = SLICE_X72Y3;

INST "QDR_Interface_B/cal_inst/hxSampReg0" LOC = SLICE_X74Y0;

NET "QDR_Interface_B/cal_inst/clkDiv2" MAXDELAY = 600 ps;
NET "QDR_Interface_B/cal_inst/phClkDiv2" MAXDELAY = 600 ps;

INST "QDR_Interface_B/cal_inst/cal_suClkd2" LOC = SLICE_X72Y4;
INST "QDR_Interface_B/cal_inst/cal_suPhClkd2" LOC = SLICE_X74Y5;
INST "QDR_Interface_B/cal_inst/phSampReg0" LOC = SLICE_X74Y4;

NET "QDR_Interface_B/cal_inst/suClkDiv2" MAXDELAY = 600ps;
NET "QDR_Interface_B/cal_inst/suPhClkDiv2" MAXDELAY = 700ps;

# NET "QDR_Interface_B/QDR_R_n_ext_stage1" MAXDELAY = 1200ps;

#############################################################
# LUT Location Constraints for cq_delay Circuit
#############################################################

INST "QDR_Interface_B/cal_inst/ckt_to_cal/one" LOC = SLICE_X74Y2;
INST "QDR_Interface_B/cal_inst/ckt_to_cal/one" BEL = F;

INST "QDR_Interface_B/cal_inst/ckt_to_cal/two" LOC = SLICE_X74Y3;
INST "QDR_Interface_B/cal_inst/ckt_to_cal/two" BEL = F;
INST "QDR_Interface_B/cal_inst/ckt_to_cal/three" LOC = SLICE_X74Y3;
INST "QDR_Interface_B/cal_inst/ckt_to_cal/three" BEL = G;

INST "QDR_Interface_B/cal_inst/ckt_to_cal/four" LOC = SLICE_X75Y2;
INST "QDR_Interface_B/cal_inst/ckt_to_cal/four" BEL = F;
INST "QDR_Interface_B/cal_inst/ckt_to_cal/five" LOC = SLICE_X75Y2;
INST "QDR_Interface_B/cal_inst/ckt_to_cal/five" BEL = G;

INST "QDR_Interface_B/cal_inst/ckt_to_cal/six" LOC = SLICE_X75Y3;
INST "QDR_Interface_B/cal_inst/ckt_to_cal/six" BEL = G;

###################################################################################
## FIFO read and write address maxdelay contraint
###################################################################################

 NET "QDR_Interface_B/Read_data_path/fifo_*_wr_addr*"  MAXDELAY = 3000ps;
 NET "QDR_Interface_B/Read_data_path/fifo_*_rd_addr*"  MAXDELAY = 3000ps;
 
 NET "QDR_Interface_B/Read_data_path/fbit_0(*)" MAXDELAY = 1200ps;
 NET "QDR_Interface_B/Read_data_path/fbit_1(*)" MAXDELAY = 1200ps;
 NET "QDR_Interface_B/Read_data_path/fbit_2(*)" MAXDELAY = 1200ps;
 NET "QDR_Interface_B/Read_data_path/fbit_3(*)" MAXDELAY = 1200ps;
 

#############################################################