代码搜索：CPLD FPGA
找到约 10,000 项符合「CPLD FPGA」的源代码
代码结果 10,000
www.eeworm.com/read/119592/14825949
h epphal.h
/*
//*************************************************************************
//
// P H I L I P S P R O P R I E T A R Y
//
// COPYRIGHT (c) 1997 BY
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h dtm_v3.h
/*----------------------------------------------------------------------------
* DTM66V Version3.0 Board Head File
*--------------------------------------------------------------------------
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vhd extension.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY extension IS
PORT (
arm_data : inout std_logic_vector(7 downto 0);
cpu_addr : in std_logic_vector(15 down
www.eeworm.com/read/436752/1845006
gfl ps2.gfl
# XST (Creating Lso File) :
fpga_40Aps2.lso
# xst flow : RunXST
fpga_40Aps2.syr
fpga_40Aps2.prj
fpga_40Aps2.sprj
fpga_40Aps2.ana
fpga_40Aps2.stx
fpga_40Aps2.cmd_log
fpga_40Aps2.ngc
fpga_40A
www.eeworm.com/read/168050/9940950
v cpu_model.v
/*========================================================== *\
Filename : Tb_fpiu_cpld.v
Author : lvchun
Description : The testbench for fpiu_cpld
Called by
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jid footpresure.jid
. CPLD_MPU1 footvhdl.vhd e:\raflfile\sd\cpld\footvhdl.vhd
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hier_info config_controller.hier_info
|config_controller
cpld_clkosc => shift_register:u4.clock
cpld_clkosc => data_bit_counter:u3.clock
cpld_clkosc => address_counter:u2.clock
cpld_clkosc => dclk_divider:u1.clock
cpld_clkosc => u5.C
www.eeworm.com/read/17749/755432
xrf kkd_modelsim.xrf
vendor_name = ModelSim
source_file = 1, E:/for_extent/test_cpld_1/test_cpld/kkd.bdf
source_file = 1, E:/for_extent/test_cpld_1/test_cpld/com_to_lpt.v
source_file = 1, E:/for_extent/test_cpld_1/test
www.eeworm.com/read/329969/12922786
cmd pcm.cmd
STYFILENAME: getpcmdata.sty
PROJECT: PCM
WORKING_PATH: "d:/cpld/fpga/getpcm"
MODULE: PCM
VHDL_FILE_LIST: "D:/ispTOOLS7_0/ispcpld/../cae_library/synthesis/vhdl/XP2.vhd" pcm.vhd
OUTPUT_FILE_NAME: P
www.eeworm.com/read/390980/8429997