config_controller.hier_info

用VHDL硬件描述语言实现的对FPGA（Cyclone II）的配置的VHDL源代码。

|config_controller
cpld_clkosc => shift_register:u4.clock
cpld_clkosc => data_bit_counter:u3.clock
cpld_clkosc => address_counter:u2.clock
cpld_clkosc => dclk_divider:u1.clock
cpld_clkosc => u5.CLK
cpld_clkosc => u6.CLK
cpld_clkosc => u7.CLK
cpld_clkosc => u8.CLK
cpld_clkosc => u9.CLK
cpld_clkosc => u10.CLK
cpld_clkosc => u11.CLK
cpld_clkosc => u12.CLK
cpld_clkosc => u13.CLK
reset_n => not_reset_n.IN0
reset_n => u5.PRESET
status_n => eek_an_error_d~0.IN0
status_n => state_error_d~0.IN0
status_n => not_status_n.IN0
flash_a22 <= u14.DB_MAX_OUTPUT_PORT_TYPE
flash_a21 <= u15.DB_MAX_OUTPUT_PORT_TYPE
flash_a20 <= u16.DB_MAX_OUTPUT_PORT_TYPE
a[0] <= u36.DB_MAX_OUTPUT_PORT_TYPE
a[1] <= u35.DB_MAX_OUTPUT_PORT_TYPE
a[2] <= u34.DB_MAX_OUTPUT_PORT_TYPE
a[3] <= u33.DB_MAX_OUTPUT_PORT_TYPE
a[4] <= u32.DB_MAX_OUTPUT_PORT_TYPE
a[5] <= u31.DB_MAX_OUTPUT_PORT_TYPE
a[6] <= u30.DB_MAX_OUTPUT_PORT_TYPE
a[7] <= u29.DB_MAX_OUTPUT_PORT_TYPE
a[8] <= u28.DB_MAX_OUTPUT_PORT_TYPE
a[9] <= u27.DB_MAX_OUTPUT_PORT_TYPE
a[10] <= u26.DB_MAX_OUTPUT_PORT_TYPE
a[11] <= u25.DB_MAX_OUTPUT_PORT_TYPE
a[12] <= u24.DB_MAX_OUTPUT_PORT_TYPE
a[13] <= u23.DB_MAX_OUTPUT_PORT_TYPE
a[14] <= u22.DB_MAX_OUTPUT_PORT_TYPE
a[15] <= u21.DB_MAX_OUTPUT_PORT_TYPE
a[16] <= u20.DB_MAX_OUTPUT_PORT_TYPE
a[17] <= u19.DB_MAX_OUTPUT_PORT_TYPE
a[18] <= u18.DB_MAX_OUTPUT_PORT_TYPE
a[19] <= u17.DB_MAX_OUTPUT_PORT_TYPE
D[0] => data0~0.IN0
D[1] => shift_register:u4.data[0]
D[2] => shift_register:u4.data[1]
D[3] => shift_register:u4.data[2]
D[4] => shift_register:u4.data[3]
D[5] => shift_register:u4.data[4]
D[6] => shift_register:u4.data[5]
D[7] => shift_register:u4.data[6]
pld_data0 <= u41.DB_MAX_OUTPUT_PORT_TYPE
config_n <= u42.DB_MAX_OUTPUT_PORT_TYPE
config_done => state_done_d.IN0
config_done => state_counting_d~0.IN0
DCLK <= u40.DB_MAX_OUTPUT_PORT_TYPE
flash_cs_n <= u37.DB_MAX_OUTPUT_PORT_TYPE
flash_oe_n <= u38.DB_MAX_OUTPUT_PORT_TYPE
flash_rw_n <= u39.DB_MAX_OUTPUT_PORT_TYPE
flash_reset_n <= flash_reset_n~0.DB_MAX_OUTPUT_PORT_TYPE
pld_msel0 <= pld_msel0~2.DB_MAX_OUTPUT_PORT_TYPE
pld_msel1 <= <GND>
loading_led <= loading_led~3.DB_MAX_OUTPUT_PORT_TYPE
error_led <= u8.DB_MAX_OUTPUT_PORT_TYPE
user_led <= user_led~0.DB_MAX_OUTPUT_PORT_TYPE


|config_controller|dclk_divider:u1
clock => lpm_counter:lpm_counter_component.clock
aclr => lpm_counter:lpm_counter_component.aclr
q[0] <= lpm_counter:lpm_counter_component.q[0]
q[1] <= lpm_counter:lpm_counter_component.q[1]
q[2] <= lpm_counter:lpm_counter_component.q[2]
q[3] <= lpm_counter:lpm_counter_component.q[3]
cout <= lpm_counter:lpm_counter_component.cout


|config_controller|dclk_divider:u1|lpm_counter:lpm_counter_component
clock => dffs[3].CLK
clock => dffs[2].CLK
clock => dffs[1].CLK
clock => dffs[0].CLK
clk_en => dffs[3].ENA
clk_en => dffs[2].ENA
clk_en => dffs[1].ENA
clk_en => dffs[0].ENA
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
aload => ~NO_FANOUT~
sset => ~NO_FANOUT~
sconst => ~NO_FANOUT~
sload => ~NO_FANOUT~
data[0] => ~NO_FANOUT~
data[1] => ~NO_FANOUT~
data[2] => ~NO_FANOUT~
data[3] => ~NO_FANOUT~
cin => and_a[0].IN1
cin => and_b[0].IN1
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffs[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffs[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffs[3].DB_MAX_OUTPUT_PORT_TYPE
eq[0] <= <GND>
eq[1] <= <GND>
eq[2] <= <GND>
eq[3] <= <GND>
eq[4] <= <GND>
eq[5] <= <GND>
eq[6] <= <GND>
eq[7] <= <GND>
eq[8] <= <GND>
eq[9] <= <GND>
eq[10] <= <GND>
eq[11] <= <GND>
eq[12] <= <GND>
eq[13] <= <GND>
eq[14] <= <GND>
eq[15] <= <GND>


|config_controller|address_counter:u2
clock => lpm_counter:lpm_counter_component.clock
clk_en => lpm_counter:lpm_counter_component.clk_en
cnt_en => lpm_counter:lpm_counter_component.cnt_en
aclr => lpm_counter:lpm_counter_component.aclr
q[0] <= lpm_counter:lpm_counter_component.q[0]
q[1] <= lpm_counter:lpm_counter_component.q[1]
q[2] <= lpm_counter:lpm_counter_component.q[2]
q[3] <= lpm_counter:lpm_counter_component.q[3]
q[4] <= lpm_counter:lpm_counter_component.q[4]
q[5] <= lpm_counter:lpm_counter_component.q[5]
q[6] <= lpm_counter:lpm_counter_component.q[6]
q[7] <= lpm_counter:lpm_counter_component.q[7]
q[8] <= lpm_counter:lpm_counter_component.q[8]
q[9] <= lpm_counter:lpm_counter_component.q[9]
q[10] <= lpm_counter:lpm_counter_component.q[10]
q[11] <= lpm_counter:lpm_counter_component.q[11]
q[12] <= lpm_counter:lpm_counter_component.q[12]
q[13] <= lpm_counter:lpm_counter_component.q[13]
q[14] <= lpm_counter:lpm_counter_component.q[14]
q[15] <= lpm_counter:lpm_counter_component.q[15]
q[16] <= lpm_counter:lpm_counter_component.q[16]
q[17] <= lpm_counter:lpm_counter_component.q[17]
q[18] <= lpm_counter:lpm_counter_component.q[18]
q[19] <= lpm_counter:lpm_counter_component.q[19]
cout <= lpm_counter:lpm_counter_component.cout


|config_controller|address_counter:u2|lpm_counter:lpm_counter_component
clock => dffs[19].CLK
clock => dffs[18].CLK
clock => dffs[17].CLK
clock => dffs[16].CLK
clock => dffs[15].CLK
clock => dffs[14].CLK
clock => dffs[13].CLK
clock => dffs[12].CLK
clock => dffs[11].CLK
clock => dffs[10].CLK
clock => dffs[9].CLK
clock => dffs[8].CLK
clock => dffs[7].CLK
clock => dffs[6].CLK
clock => dffs[5].CLK
clock => dffs[4].CLK
clock => dffs[3].CLK
clock => dffs[2].CLK
clock => dffs[1].CLK
clock => dffs[0].CLK
clk_en => dffs[19].ENA
clk_en => dffs[18].ENA
clk_en => dffs[17].ENA
clk_en => dffs[16].ENA
clk_en => dffs[15].ENA
clk_en => dffs[14].ENA
clk_en => dffs[13].ENA
clk_en => dffs[12].ENA
clk_en => dffs[11].ENA
clk_en => dffs[10].ENA
clk_en => dffs[9].ENA
clk_en => dffs[8].ENA
clk_en => dffs[7].ENA
clk_en => dffs[6].ENA
clk_en => dffs[5].ENA
clk_en => dffs[4].ENA
clk_en => dffs[3].ENA
clk_en => dffs[2].ENA
clk_en => dffs[1].ENA
clk_en => dffs[0].ENA
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
aload => ~NO_FANOUT~
sset => ~NO_FANOUT~
sconst => ~NO_FANOUT~
sload => ~NO_FANOUT~
data[0] => ~NO_FANOUT~
data[1] => ~NO_FANOUT~
data[2] => ~NO_FANOUT~
data[3] => ~NO_FANOUT~
data[4] => ~NO_FANOUT~
data[5] => ~NO_FANOUT~
data[6] => ~NO_FANOUT~
data[7] => ~NO_FANOUT~
data[8] => ~NO_FANOUT~
data[9] => ~NO_FANOUT~
data[10] => ~NO_FANOUT~
data[11] => ~NO_FANOUT~
data[12] => ~NO_FANOUT~
data[13] => ~NO_FANOUT~
data[14] => ~NO_FANOUT~
data[15] => ~NO_FANOUT~
data[16] => ~NO_FANOUT~
data[17] => ~NO_FANOUT~
data[18] => ~NO_FANOUT~
data[19] => ~NO_FANOUT~
cin => and_a[0].IN1
cin => and_b[0].IN1
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffs[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffs[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffs[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffs[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= dffs[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= dffs[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= dffs[7].DB_MAX_OUTPUT_PORT_TYPE
q[8] <= dffs[8].DB_MAX_OUTPUT_PORT_TYPE
q[9] <= dffs[9].DB_MAX_OUTPUT_PORT_TYPE
q[10] <= dffs[10].DB_MAX_OUTPUT_PORT_TYPE
q[11] <= dffs[11].DB_MAX_OUTPUT_PORT_TYPE
q[12] <= dffs[12].DB_MAX_OUTPUT_PORT_TYPE
q[13] <= dffs[13].DB_MAX_OUTPUT_PORT_TYPE
q[14] <= dffs[14].DB_MAX_OUTPUT_PORT_TYPE
q[15] <= dffs[15].DB_MAX_OUTPUT_PORT_TYPE
q[16] <= dffs[16].DB_MAX_OUTPUT_PORT_TYPE
q[17] <= dffs[17].DB_MAX_OUTPUT_PORT_TYPE
q[18] <= dffs[18].DB_MAX_OUTPUT_PORT_TYPE
q[19] <= dffs[19].DB_MAX_OUTPUT_PORT_TYPE
eq[0] <= <GND>
eq[1] <= <GND>
eq[2] <= <GND>
eq[3] <= <GND>
eq[4] <= <GND>
eq[5] <= <GND>
eq[6] <= <GND>
eq[7] <= <GND>
eq[8] <= <GND>
eq[9] <= <GND>
eq[10] <= <GND>
eq[11] <= <GND>
eq[12] <= <GND>
eq[13] <= <GND>
eq[14] <= <GND>
eq[15] <= <GND>


|config_controller|data_bit_counter:u3
clock => lpm_counter:lpm_counter_component.clock
clk_en => lpm_counter:lpm_counter_component.clk_en
cnt_en => lpm_counter:lpm_counter_component.cnt_en
aclr => lpm_counter:lpm_counter_component.aclr
q[0] <= lpm_counter:lpm_counter_component.q[0]
q[1] <= lpm_counter:lpm_counter_component.q[1]
q[2] <= lpm_counter:lpm_counter_component.q[2]
cout <= lpm_counter:lpm_counter_component.cout


|config_controller|data_bit_counter:u3|lpm_counter:lpm_counter_component
clock => dffs[2].CLK
clock => dffs[1].CLK
clock => dffs[0].CLK
clk_en => dffs[2].ENA
clk_en => dffs[1].ENA
clk_en => dffs[0].ENA
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
aload => ~NO_FANOUT~
sset => ~NO_FANOUT~
sconst => ~NO_FANOUT~
sload => ~NO_FANOUT~
data[0] => ~NO_FANOUT~
data[1] => ~NO_FANOUT~
data[2] => ~NO_FANOUT~
cin => and_a[0].IN1
cin => and_b[0].IN1
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffs[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffs[2].DB_MAX_OUTPUT_PORT_TYPE
eq[0] <= <GND>
eq[1] <= <GND>
eq[2] <= <GND>
eq[3] <= <GND>
eq[4] <= <GND>
eq[5] <= <GND>
eq[6] <= <GND>
eq[7] <= <GND>
eq[8] <= <GND>
eq[9] <= <GND>
eq[10] <= <GND>
eq[11] <= <GND>
eq[12] <= <GND>
eq[13] <= <GND>
eq[14] <= <GND>
eq[15] <= <GND>


|config_controller|shift_register:u4
clock => lpm_shiftreg:lpm_shiftreg_component.clock
enable => lpm_shiftreg:lpm_shiftreg_component.enable
load => lpm_shiftreg:lpm_shiftreg_component.load
aclr => lpm_shiftreg:lpm_shiftreg_component.aclr
data[0] => lpm_shiftreg:lpm_shiftreg_component.data[0]
data[1] => lpm_shiftreg:lpm_shiftreg_component.data[1]
data[2] => lpm_shiftreg:lpm_shiftreg_component.data[2]
data[3] => lpm_shiftreg:lpm_shiftreg_component.data[3]
data[4] => lpm_shiftreg:lpm_shiftreg_component.data[4]
data[5] => lpm_shiftreg:lpm_shiftreg_component.data[5]
data[6] => lpm_shiftreg:lpm_shiftreg_component.data[6]
shiftout <= lpm_shiftreg:lpm_shiftreg_component.shiftout


|config_controller|shift_register:u4|lpm_shiftreg:lpm_shiftreg_component
clock => dffs[6].CLK
clock => dffs[5].CLK
clock => dffs[4].CLK
clock => dffs[3].CLK
clock => dffs[2].CLK
clock => dffs[1].CLK
clock => dffs[0].CLK
enable => dffs[6].ENA
enable => dffs[5].ENA
enable => dffs[4].ENA
enable => dffs[3].ENA
enable => dffs[2].ENA
enable => dffs[1].ENA
enable => dffs[0].ENA
aset => ~NO_FANOUT~
q[0] <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= dffs[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= dffs[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= dffs[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= dffs[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= dffs[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= dffs[6].DB_MAX_OUTPUT_PORT_TYPE
shiftout <= dffs[0].DB_MAX_OUTPUT_PORT_TYPE