dtm_v3.h

AT91fr40162的FLASH读写程序

/*----------------------------------------------------------------------------
*         DTM66V Version3.0 Board Head File
*----------------------------------------------------------------------------
*  DMT-66V 手持机板的头文件
*----------------------------------------------------------------------------
* File Name           : dtm_v3.h
* Object              : DTM-66V驾驶员培训管理器手持机板定义文件.
*
* 1.0 01/Apr/04  PFi  : 创建
*----------------------------------------------------------------------------
*/
#ifndef dtm_v3_h
#define dtm_v3_h

/* Internal Memory : 256K*8 */
#define RAM_BASE     		(0x00300000)    			/* 0x00000000 Address of the Internal SRAM after the remap command */
#define RAM_SIZE     		(256*1024)
#define RAM_LIMIT     		(RAM_BASE + (8*1024))       /* Size of the Application stack is 8K. */


/*---------------------------------------*/
/*  External Memories Definition 		 */
/*---------------------------------------*/

/* Flash Memory : AT49BV1614 512K*16 */
#define FLASH_BASE      	(0x01000000)						// 0x01000000
#define FLASH_SIZE      	(2*1024*1024)                		/* byte */

/* Extern Memory : 256K*16 */
#define EXT_SRAM_BASE       (0x00400000)                		/* 外部存储器的地址 */
#define EXT_SRAM_SIZE       (2*256*1024)        				/* 4M bit,512KB */
#define EXT_SRAM_LIMIT      (EXT_RAM_BASE + EXT_RAM_SIZE)       /* = SRAM_LIMIT = 0x40000 */

/* CPLD Extern Memory : 1*16 */
#define CPLD_MEM_BASE       (0x20000000)                		/* 外部存储器的地址 */
#define CPLD_MEM_SIZE       (1*16)        						/* 最多8个寄存器,A0未使用 */
#define CPLD_MEM_LIMIT      (CPLD_MEM_BASE + CPLD_MEM_SIZE)     /* = SRAM_LIMIT = 0x10 */

/* BCT Extern Memory : 1*64 */
#define BCT_MEM_BASE       	(0x30000000)                		/* 外部存储器的地址 */
#define BCT_MEM_SIZE       	(1*64)        						/* 最多8个寄存器,A0未使用 */
#define BCT_MEM_LIMIT      	(BCT_MEM_BASE + BCT_MEM_SIZE)     	/* = SRAM_LIMIT = 0x10 */


/*---------------------------------------*/
/*  Memories Map Definition 		 	 */
/*---------------------------------------*/
#define EBI_CSR_0       ((unsigned int )(FLASH_BASE    | 0x273d))   /* 0x01000000, 16MB, 2 tdf, 16 bits, 7 WS  */
#define EBI_CSR_1       ((unsigned int )(EXT_SRAM_BASE | 0x3021))   /* 0x00400000, 1MB,16 bit,0 WS */
#define EBI_CSR_2       ((unsigned int )(CPLD_MEM_BASE | 0x2022))   /* 0x00800000, 1MB,8 bit,0 WS  */
#define EBI_CSR_3       ((unsigned int )(BCT_MEM_BASE  | 0x2e3e))   /* 0x00a00000, 1MB, 7 tdf, 8 bit, 7 WS */
#define EBI_CSR_4       ((unsigned int )0x40000000)               /* unused */
#define EBI_CSR_5       ((unsigned int )0x50000000)               /* unused */
#define EBI_CSR_6       ((unsigned int )0x60000000)               /* unused */
#define EBI_CSR_7       ((unsigned int )0x70000000)               /* unused */

//*---------------------------------------*/
//*    	I/O Port Definition
//*---------------------------------------*/
//*    	BCT Definition for DTM Board 
#define BCT_D0          (1<<0)	// P0
#define BCT_D1          (1<<1)	// P1
#define BCT_D2          (1<<2)	// P2
#define BCT_D3          (1<<3)	// P3
#define BCT_D4          (1<<4)	// P4
#define BCT_D5          (1<<5)	// P5
#define BCT_D6          (1<<6)	// P6
#define BCT_D7          (1<<7)	// P7
#define BCT_DSC      	(1<<8)	// P8
#define BCT_SED      	(1<<15)	// P15
#define BCT_END_SH      (1<<16)	// P16
#define BCT_RESET       (1<<17)	// P17
#define BCT_WE          (1<<18)	// P18
#define BCT_SLEEP       (1<<25)	// P25
#define BCT_CE          (1<<27)	// P27
#define BCT_ABUS4       0x8000	//(1<<31)	// P31

//*   	EXT Singal Definition 
#define EXTIRQ0			((unsigned int) 0x01 << 16)	// IRQ0
#define EXTINT			(1 << 9)	// P9


//*    	BLP PUSH SWITCH for DTM Board 
#define SW1				(1<<10)	// P10
#define SW1_MASK		(1<<10) 

//*   	Key Definition 
#define KEY1			(1<<11)	// P11
#define KEY2			(1<<12)	// P12
#define KEY3			(1<<13)	// P13
#define KEY4			(1<<14)	// P14
//* 	Push Buttons MASK 
#define KEY1_MASK       (1<<11)
#define KEY2_MASK       (1<<12)
#define KEY3_MASK       (1<<13)
#define KEY4_MASK       (1<<14)
#define KEY_MASK        (KEY1_MASK|KEY2_MASK|KEY3_MASK|KEY4_MASK)

//*   	Serial EEPROM Definition 
#define SCL             (1<<19)	// P19
#define SDA             (1<<20)	// P20
#define PIO_SCL         (1<<19)	
#define PIO_SDA         (1<<20)

//*   	UTRA Definition
#define ARMTXD1			(1<<21)	// P21
#define ARMRXD1			(1<<22)	// P22

//*   	IC INSERT CHECK Definition
#define IC_IN           (1<<23)	// P23

//*    	HT1380 Definition
#define HTRST          	(1<<2) // P24
#define HTSDA           (1<<29)	// P29
#define HTSCL           (1<<30)	// P30
#define PIO_HTRST       (1<<24)
#define PIO_HTSCL       (1<<29)	
#define PIO_HTSDA       (1<<30)

/*   EXT Power Definition */
#define EXTPWD			(1<<1)	// P28


/*    Master Clock 	*/
#define MCK             66000000
#define MCKKHz          (MCK/1000)


#endif /* dtm_v3_h */