ps2.gfl

一些接口电路的Verilog设计

# XST (Creating Lso File) : 
fpga_40Aps2.lso
# xst flow : RunXST
fpga_40Aps2.syr
fpga_40Aps2.prj
fpga_40Aps2.sprj
fpga_40Aps2.ana
fpga_40Aps2.stx
fpga_40Aps2.cmd_log
fpga_40Aps2.ngc
fpga_40Aps2.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
e:\工程中心培训\※※※数字培训\第一阶段－verilog建模\verilog基本例子\basic2\ps2\ise\ps2/_ngo
fpga_40Aps2.ngd
fpga_40Aps2_ngdbuild.nav
fpga_40Aps2.bld
fpga_40Aps2.ucf.untf
fpga_40Aps2.cmd_log
# Implementation : Map
fpga_40Aps2_map.ncd
fpga_40Aps2.ngm
fpga_40Aps2.pcf
fpga_40Aps2.nc1
fpga_40Aps2.mrp
fpga_40Aps2_map.mrp
fpga_40Aps2.mdf
__projnav/map.log
fpga_40Aps2.cmd_log
MAP_NO_GUIDE_FILE_CPF "fpga_40Aps2"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
fpga_40Aps2.twr
fpga_40Aps2.twx
fpga_40Aps2.tsi
fpga_40Aps2.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
fpga_40Aps2.ncd
fpga_40Aps2.par
fpga_40Aps2.pad
fpga_40Aps2_pad.txt
fpga_40Aps2_pad.csv
fpga_40Aps2.pad_txt
fpga_40Aps2.dly
reportgen.log
fpga_40Aps2.xpi
fpga_40Aps2.grf
fpga_40Aps2.itr
fpga_40Aps2_last_par.ncd
__projnav/par.log
fpga_40Aps2.placed_ncd_tracker
fpga_40Aps2.routed_ncd_tracker
fpga_40Aps2.cmd_log
PAR_NO_GUIDE_FILE_CPF "fpga_40Aps2"
# Implementation : Generate Post-Par Simulation Model
fpga_40Aps2_timesim.v
fpga_40Aps2_timesim.sdf
fpga_40Aps2_timesim.sdf
fpga_40Aps2_timesim.v
fpga_40Aps2_timesim.nlf
fpga_40Aps2.par_nlf
fpga_40Aps2.versim_par
fpga_40Aps2.cmd_log
__projnav/netgen_par_tcl.rsp
# XST (Creating Lso File) : 
reset.lso
# xst flow : RunXST
reset.syr
reset.prj
reset.sprj
reset.ana
reset.stx
reset.cmd_log
reset.ngc
reset.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
e:\※※※硬件描述语言与数字系统设计\※※※本科教学—硬件描述语言与数字系统设计\※※※郑朝霞-上课讲义\ppt\fpga设计实例\ps2\ise\ps2/_ngo
reset.ngd
reset_ngdbuild.nav
reset.bld
.untf
reset.cmd_log
# Assign Package Pins
__projnav/parentAssignPackagePinsApp_tcl.rsp
# Implementation : Generate Post-Translate Simulation Model
reset_translate.v
reset_translate.v
reset_translate.nlf
reset.xlate_nlf
reset.versim_xlate
reset.cmd_log
# Implementation : Map
reset_map.ncd
reset.ngm
reset.pcf
reset.nc1
reset.mrp
reset_map.mrp
reset.mdf
__projnav/map.log
reset.cmd_log
MAP_NO_GUIDE_FILE_CPF "reset"
# Implmentation : Post-Map Static Timing
__projnav/pretrc.log
reset_preroute.twr
reset_preroute.twx
reset.twx_map
reset.tsi
reset.tw1
reset.cmd_log
# Implmentation : Post-Map Static Timing Report
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
reset.twr
reset.twx
reset.tsi
reset.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
reset.ncd
reset.par
reset.pad
reset_pad.txt
reset_pad.csv
reset.pad_txt
reset.dly
reportgen.log
reset.xpi
reset.grf
reset.itr
reset_last_par.ncd
__projnav/par.log
reset.placed_ncd_tracker
reset.routed_ncd_tracker
reset.cmd_log
PAR_NO_GUIDE_FILE_CPF "reset"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
reset.twr
reset.twx
reset.tsi
reset.cmd_log
# Implementation : Generate Post-Par Simulation Model
reset_timesim.v
reset_timesim.sdf
reset_timesim.sdf
reset_timesim.v
reset_timesim.nlf
reset.par_nlf
reset.versim_par
reset.cmd_log
__projnav/netgen_par_tcl.rsp
# View RTL Schematic
fpga_40Aps2.ngr
# XST (Creating Lso File) : 
fpga_40Aps2.lso
# xst flow : RunXST
fpga_40Aps2.syr
fpga_40Aps2.prj
fpga_40Aps2.sprj
fpga_40Aps2.ana
fpga_40Aps2.stx
fpga_40Aps2.cmd_log
reset.ngc
fpga_40Aps2.ngc
reset.ngr
fpga_40Aps2.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
e:\※※※硬件描述语言与数字系统设计\※※※本科教学—硬件描述语言与数字系统设计\※※※郑朝霞-上课讲义\ppt\fpga设计实例\ps2\ise\ps2/_ngo
fpga_40Aps2.ngd
fpga_40Aps2_ngdbuild.nav
fpga_40Aps2.bld
fpga_40Aps2.ucf.untf
fpga_40Aps2.cmd_log
# Implementation : Map
fpga_40Aps2_map.ncd
fpga_40Aps2.ngm
fpga_40Aps2.pcf
fpga_40Aps2.nc1
fpga_40Aps2.mrp
fpga_40Aps2_map.mrp
fpga_40Aps2.mdf
__projnav/map.log
fpga_40Aps2.cmd_log
MAP_NO_GUIDE_FILE_CPF "fpga_40Aps2"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
fpga_40Aps2.twr
fpga_40Aps2.twx
fpga_40Aps2.tsi
fpga_40Aps2.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
fpga_40Aps2.ncd
fpga_40Aps2.par
fpga_40Aps2.pad
fpga_40Aps2_pad.txt
fpga_40Aps2_pad.csv
fpga_40Aps2.pad_txt
fpga_40Aps2.dly
reportgen.log
fpga_40Aps2.xpi
fpga_40Aps2.grf
fpga_40Aps2.itr
fpga_40Aps2_last_par.ncd
__projnav/par.log
fpga_40Aps2.placed_ncd_tracker
fpga_40Aps2.routed_ncd_tracker
fpga_40Aps2.cmd_log
PAR_NO_GUIDE_FILE_CPF "fpga_40Aps2"
# XST (Creating Lso File) : 
fpga_40Aps2.lso
# xst flow : RunXST
fpga_40Aps2.syr
fpga_40Aps2.prj
fpga_40Aps2.sprj
fpga_40Aps2.ana
fpga_40Aps2.stx
fpga_40Aps2.cmd_log
reset.ngc
fpga_40Aps2.ngc
reset.ngr
fpga_40Aps2.ngr
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
e:\※※※硬件描述语言与数字系统设计\※※※本科教学—硬件描述语言与数字系统设计\※※※郑朝霞-上课讲义\ppt\fpga设计实例\ps2\ise\ps2/_ngo
fpga_40Aps2.ngd
fpga_40Aps2_ngdbuild.nav
fpga_40Aps2.bld
fpga_40Aps2.ucf.untf
fpga_40Aps2.cmd_log
# Implementation : Map
fpga_40Aps2_map.ncd
fpga_40Aps2.ngm
fpga_40Aps2.pcf
fpga_40Aps2.nc1
fpga_40Aps2.mrp
fpga_40Aps2_map.mrp
fpga_40Aps2.mdf
__projnav/map.log
fpga_40Aps2.cmd_log
MAP_NO_GUIDE_FILE_CPF "fpga_40Aps2"
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
fpga_40Aps2.twr
fpga_40Aps2.twx
fpga_40Aps2.tsi
fpga_40Aps2.cmd_log
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
fpga_40Aps2.ncd
fpga_40Aps2.par
fpga_40Aps2.pad
fpga_40Aps2_pad.txt
fpga_40Aps2_pad.csv
fpga_40Aps2.pad_txt
fpga_40Aps2.dly
reportgen.log
fpga_40Aps2.xpi
fpga_40Aps2.grf
fpga_40Aps2.itr
fpga_40Aps2_last_par.ncd
__projnav/par.log
fpga_40Aps2.placed_ncd_tracker
fpga_40Aps2.routed_ncd_tracker
fpga_40Aps2.cmd_log
PAR_NO_GUIDE_FILE_CPF "fpga_40Aps2"
# Implementation : Generate Post-Par Simulation Model
fpga_40Aps2_timesim.v
fpga_40Aps2_timesim.sdf
fpga_40Aps2_timesim.sdf
fpga_40Aps2_timesim.v
fpga_40Aps2_timesim.nlf
fpga_40Aps2.par_nlf
fpga_40Aps2.versim_par
fpga_40Aps2.cmd_log
__projnav/netgen_par_tcl.rsp
# Generate Programming File
__projnav/fpga_40Aps2_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
fpga_40Aps2.ut
# Programming File Generation Report
fpga_40Aps2.bgn
fpga_40Aps2.rbt
fpga_40Aps2.ll
fpga_40Aps2.msk
fpga_40Aps2.drc
fpga_40Aps2.nky
fpga_40Aps2.bit
fpga_40Aps2.bin
fpga_40Aps2.isc
fpga_40Aps2.cmd_log
# Configure Device (iMPACT)
fpga_40Aps2.prm
fpga_40Aps2.isc
fpga_40Aps2.svf
xilinx.sys
fpga_40Aps2.mcs
fpga_40Aps2.exo
fpga_40Aps2.hex
fpga_40Aps2.tek
fpga_40Aps2.dst
fpga_40Aps2.dst_compressed
fpga_40Aps2.mpm
_impact.cmd
_impact.log