cpu_model.v

Verilog HDL编写的CPU模型

/*========================================================== *\
         Filename  : Tb_fpiu_cpld.v
          Author   : lvchun
      Description  : The testbench for fpiu_cpld
        Called by  : 
 Revision History  :mm/dd/yy
                    Revision 1.0
            Email  :[e-mail]
          Company  :Huawei Technology .Inc
Copyright(c) 1999, Huawei Technology Inc, All right reserved
\* ========================================================= */
module CPU_BFM(
               Int,
               
               Rd,
               Wr,
               Cs,
               Addr,
               
               Data
               );
               
input          Int;

output         Rd;
output         Wr;
output         Cs;
output [2:0]   Addr;

inout  [3:0]   Data;               

//internal register decalaration
reg            Mcop;//The cpu bus operation flag
reg    [2:0]   Write_addr;
reg    [3:0]   Write_data;
reg    [2:0]   Read_addr;
reg    [3:0]   Read_data;

reg    [3:0]   Unvoltage_reg;
reg            Fuse_reg;

reg            Clk;
reg            Rst;

wire   [2:0]   Addr;
wire   [3:0]   Data;

integer        i;

parameter      MODEL_SELECT = 0;
/*=============================================================================*\
                          Call the Cpu bfm
\*=============================================================================*/                          
cfgbfm Ucfgbfm(
	.Clk(Clk),			//reference Clk, input
	.Rst(Rst),			//0,reset,input
	
	.INT_n(Int),			//0,interrupt requst,input
	.Intel_Moto(Intel_Moto),        //0,intel;1,motorola;BTS,output
	.Rd_Wr_CPU_n(Rd),               //Intel_RD_n or Moto_RW_n,output
	.Wr_Ds_CPU_n(Wr),               //Intel_WR_n or Moto_DS_n,output
	.CS_n(Cs),			//0,select
	.Addr(Addr),			//output
	.Data(Data)			//inout
	);
	
//Define the cpu bfm
assign Intel_Moto = 1'b1;//The bus is intel model

defparam Ucfgbfm.ADDRSIZE = 3;//Define the address bus wideth
defparam Ucfgbfm.DATASIZE = 4;//Define the data bus wideth

defparam Ucfgbfm.t1 = 1;
defparam Ucfgbfm.t2 = 1;
defparam Ucfgbfm.t3 = 27;
defparam Ucfgbfm.t4 = 5;
defparam Ucfgbfm.t5 = 1;
defparam Ucfgbfm.t6 = 65;
defparam Ucfgbfm.t7 = 65;
defparam Ucfgbfm.t8 = 15;
defparam Ucfgbfm.t9 = 5;

//Create clock
always 
  #(Ucfgbfm.CYCLE/2) Clk= ~Clk;

//Create Reset single for cpu
initial 
begin
                       Clk = 1'b0;
                       Rst<= 1'b1;
#(30*Ucfgbfm.CYCLE)    Rst<= 1'b0;
end

//Initial operation
initial
begin
   wait(~Rst);
   Mcop = 1'b0;//Give the initial value of the cpu bus operation flag
   Read_data = 4'b0;
   Ucfgbfm.Intel_Moto_mode_select(MODEL_SELECT);//Define the cpu bus model is intel
   Write_addr = 3'b010;
   Write_data = 4'b0010;
   Ucfgbfm.write_reg(Write_addr,Write_data);
   Write_addr = 3'b011;
   Write_data = 4'b0001;
   Ucfgbfm.write_reg(Write_addr,Write_data);//The softreset
   Write_addr = 3'b001;
   for(i=0;i<=7;i=i+1)
   begin
       Write_data = i;
       Ucfgbfm.write_reg(Write_addr,Write_data);
   end//Output the address of DS1624
   for(i=0;i<=3;i=i+1)
   begin
       Read_addr = i;
       Ucfgbfm.read_reg(Read_addr,Read_data);
   end//Read operation
   Mcop = 1'b1;
end

//The alarm detect
always
begin
   wait(Mcop);
   Read_addr = 3'b0;
   Ucfgbfm.read_reg(Read_addr,Read_data);
   Unvoltage_reg = Read_data;
   Read_addr = 3'b011;
   Ucfgbfm.read_reg(Read_addr,Read_data);
   Fuse_reg = Read_data[1];
end      
endmodule