代码搜索：CPLD FPGA
找到约 10,000 项符合「CPLD FPGA」的源代码
代码结果 10,000
www.eeworm.com/read/447999/7542282
log coregen.log
# Xilinx CORE Generator 6.3i
# User = Administrator
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in G:\vijay_FPGA_LAB\4bit_alu\coregen.log
# busformat
www.eeworm.com/read/447996/7542328
lfp alu_2bit.lfp
# begin LFP file G:\vijay_FPGA_LAB\alu_2bit\alu_2bit.lfp
designfile alu_2bit.ngd
IO_GROUP "sout" IO_GROUP="alu_2bit" ;
IO_GROUP "dis_out" IO_GROUP="alu_2bit" ;
IO_GROUP "bin" IO_GROUP="alu_2bit" ;
www.eeworm.com/read/443860/7621554
cmd_log can_top.cmd_log
xst -intstyle ise -ifn __projnav/can_top.xst -ofn can_top.syr
xst -intstyle ise -ifn __projnav/can_top.xst -ofn can_top.syr
ngdbuild -intstyle ise -dd e:\program\fpga_program\for_fpga\can\ise\canbus
www.eeworm.com/read/435698/7786607
txt xiangweiji.txt
相位测量仪的分模块原理框图(以分辨率为0.1°为例)如图3-2所示。基准信号(相位基准)Fr经放大整形后加到锁相环的输入端，在锁相环的反馈环路中设置一个N=3600的分频器，使锁相环的输出信号频率为3600Fr，但相位与Fr相同，这个输出信号被用作计数器的计数时钟。被测信号Fs经整形放大再2分频后得到的Fs／2与Fr／2送入由异或门组成的相位比较电路，其输出脉冲A的脉宽Tp反映了两列信号的相位差。 ...
www.eeworm.com/read/198751/7912299
tlg pci_bridge32.tlg
Selecting top level module pci_bridge32
Synthesizing module pci_out_reg
Synthesizing module pci_rst_int
@W: CL159 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_rst_int.v":91:6:91:10|Inpu
www.eeworm.com/read/297727/8000235
qmsg 429_enc_dec.fit.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter
www.eeworm.com/read/397988/8011624
v tony_wu.v
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Shanghai Tianma Micro-Electronics Co.,Ltd.
// Engineer: Tony_Wu
// Cre
www.eeworm.com/read/329381/12957232
log cc_build_debug.log
-------------------------- fpga_loader.pjt - Debug --------------------------
[fpga_loader.cdb] "D:\CCStudio_v3.1\plugins\bios\gconfgen" fpga_loader.cdb
[boot.asm] "D:\CCStudio_v3.1\C6000\cgtool
www.eeworm.com/read/326648/13128338
qmsg txd.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:
www.eeworm.com/read/315669/13538562
tlg cmos_fifo_usb.tlg
Selecting top level module cmos_fifo_usb
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":1705:7:1705:9|Synthesizing module VCC
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib