tony_wu.v

Verilog HDL程序 Verilog HDL程序

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:        Shanghai Tianma Micro-Electronics Co.,Ltd. 
// Engineer:       Tony_Wu
// Create Date:    14:41:41 12/27/2008 
// Design Name:    TM695RDH02
// Module Name:    TM695RDH02
// Project Name:   TM695RDH02
// Target Devices: XC2S100E-6PQ208
// Tool versions:  ISE 9.1i
// Description: 
//
// Revision:       1.0
//
//////////////////////////////////////////////////////////////////////////////////
module TM695_1227(reset_key,up_key,down_key,clk,
                 lcd_dclk,lcd_de,lcd_hs,lcd_vs,r_out,g_out,b_out,
					  fpga_led0,fpga_led1,fpga_led2,power_c1,power_c3);
 
  input clk,reset_key,up_key,down_key;
  output lcd_dclk,lcd_de,lcd_hs,lcd_vs,r_out,g_out,b_out,
         fpga_led0,fpga_led1,fpga_led2,power_c1,power_c3;
  
//*************************flash*******************************  			
/*	input[15:0]  mmdata_bus;
	output flash_noe,flash_nrst,flash_nwe,flash_nwp; 
	output[3:0]  flash_ncs;
	output[20:0] mmaddress_bus; 
	
	reg[4:0]  fclk_counter;
	reg[3:0]  flash_ncs;
	reg flash_noe,flash_nrst,flash_nwe,flash_nwp; 
	reg[20:0] mmaddress_bus;
	reg[18:0] flash_addr;
	reg[17:0] picture;
	reg[15:0] output_buffer;
*/
//******************************************************************** 
  reg[5:0] r_out,g_out,b_out,rdata,gdata,bdata,rvdata,gvdata,bvdata,
            chessdata,crossdata,frdata,fgdata,fbdata,tp_one,tp_two,
				tp_three,tp_four,tp_five;
  reg lcd_dclk,lcd_de,lcd_hs,lcd_vs,fpga_led0,fpga_led1,fpga_led2; 
  reg[5:0] hgray,vgray,n,v;
//******************************************************************** 
  reg[20:0] key_clk_counter;
  reg a_flag,b_flag,c_flag,on_off,dclk_reg,power_c1,power_c3;
  reg key_clk,hs_reg,vs_reg,keyen,de_reg,dclk,vdot,hline;
  reg[3:0] pattern_num,clk_counter,m_counter;
  reg[10:0] dot_counter,line_counter;//dot_counter is the counter of Dotclk;line_counter is the counter of Hsync

//*********************parameter setting****************************************
	parameter tvpw=3;//VSYNC pulse width(tvpw):1~20 H,tvpw=3
	parameter tvbp=20;//VSYNC Bank porch(tvbp):tvbp=20
	parameter tvfp=22;//VSYNC Front porch(tvfp):1~77H,typ:tvfp=12H
	parameter tvb=tvpw+tvbp;//VSYNC Blanking(tvb);tvb=tvpw+tvbp=3+20=23
	parameter tvd=480+tvpw+tvbp;//Vertical display area(tvd),tvd=480
	parameter tv=480+tvpw+tvbp+tvfp;//VSYNC period time(tv),tv=523
	
	parameter thpw=6; //HSYNC pulse width(thpw):1~40 Dclk,typ:thpw=6
	parameter thbp=40;//HSYNC Bank porch(thbp):thbp=40
	parameter thfp=210;//HSYNC Front porch(thfp):thfp=210
	parameter thb=thpw+thbp;//HSYNC blanking(thb):thb=46
	parameter thd=800+thpw+thbp;//Horizontal display area(thd):thd=800
	parameter th=800+thpw+thbp+thfp;//1 Horizontal Line(th):th=1056
	
//*************************initial**********************************************
  initial
  begin
  key_clk_counter=0;
  clk_counter=0;
  a_flag=0;
  b_flag=0;
  c_flag=0;  
  on_off=0;	
  key_clk=0;		
  dot_counter=1;
  line_counter=1;
  de_reg=0;
  pattern_num=1;
  fpga_led0=0;
  fpga_led1=0;
  fpga_led2=1;

  end
//*************************Genetate key_clk=66Hz-********************************** 

always@(posedge clk)
	begin
		if(key_clk_counter==2000000) 
			key_clk_counter=0;
		else
			key_clk_counter=key_clk_counter+1;
			
		if(key_clk_counter==0)			
			key_clk=0;
		else if(key_clk_counter==1000000)
			key_clk=1;		
	end

//*************************Genetate on_off(active H),pattern_num*******************

always@(posedge key_clk)
	begin
		if(reset_key==0)		a_flag=1;
		else					   a_flag=0;
		
		if(up_key==0||reset_key==0)
				begin
				b_flag=1; 
				keyen=0;
				end
		else	 
				begin
				b_flag=0; 
		      keyen=1;
				end
	end
	
	
always@(posedge a_flag)  
	begin
		on_off=~on_off;
      power_c1=~on_off;
		power_c3=on_off;

	end


always@(posedge b_flag)
	begin
		if(on_off==0)					pattern_num<=1;
		else if(pattern_num==14)		pattern_num<=1;
				else					pattern_num<=pattern_num+1;
	end

//******************************Genetate DCLK=25MHz---------------------------*/
always@(posedge clk)
	begin
			if(clk_counter==3) //100MHZ/4=25MHZ
			clk_counter=0;
			else  clk_counter=clk_counter+1;
			if(clk_counter==0) dclk=0;
			else if(clk_counter==2)
			begin
			dclk=1;
		   end
	dclk_reg=dclk;
	end
//**********************Generate SYNC signal*******************************
always@(posedge dclk_reg)
	begin
		if(dot_counter==th)
					dot_counter<=1;
		else		dot_counter<=dot_counter+1;
		
		if(dot_counter==1)
			if(line_counter==tv)
					line_counter<=1;
			else	line_counter<=line_counter+1;
		
		if(dot_counter==th)			hs_reg<=0;
		if(dot_counter==thpw)				hs_reg<=1;
		
		if(line_counter>=thb&&line_counter<thb+480)
			begin
				if(dot_counter==tvb)			de_reg<=1;
				if(dot_counter==thd)			de_reg<=0;
			end
		else 	de_reg<=0;
		
		if(line_counter==tv)			vs_reg<=0;
		if(line_counter==tvpw)				vs_reg<=1;
		
	end
	
//*************************horizzontal color bar*************************
always@(posedge dclk_reg)
begin
     if(dot_counter>=tvb&&dot_counter<tvb+100)//black
	     begin 
	     rdata=6'b000000;
			 gdata=6'b000000;
			 bdata=6'b000000;
	     end
	  if(dot_counter>=tvb+100&&dot_counter<tvb+200)//red
	     begin 
	     rdata=6'b111111;
			 gdata=6'b000000;
			 bdata=6'b000000;
	     end
	  if(dot_counter>=tvb+200&&dot_counter<tvb+300)//yellow
	     begin 
	     rdata=6'b111111;
			 gdata=6'b111111;
			 bdata=6'b000000;
	     end
	  if(dot_counter>=tvb+300&&dot_counter<tvb+400)//green
	     begin 
	     rdata=6'b000000;
			 gdata=6'b111111;
			 bdata=6'b000000;
	     end
	  if(dot_counter>=tvb+400&&dot_counter<tvb+500)//cyan
	     begin 
	     rdata=6'b000000;
			 gdata=6'b111111;
			 bdata=6'b111111;
	     end
		if(dot_counter>=tvb+500&&dot_counter<tvb+600)//blue
	     begin 
	     rdata=6'b000000;
			 gdata=6'b000000;
			 bdata=6'b111111;
	     end
      if(dot_counter>=tvb+600&&dot_counter<tvb+700)//magenta
	     begin 
	     rdata=6'b111111;
			 gdata=6'b000000;
			 bdata=6'b111111;
	     end
		if(dot_counter>=tvb+700&&dot_counter<thd)//white
	     begin 
	     rdata=6'b111111;
			 gdata=6'b111111;
			 bdata=6'b111111;
	     end
end
//*******************vertical color bar***************************
always@(posedge dclk_reg)
begin
     if(line_counter>=thb&&line_counter<thb+60)//black
	    begin
	   rvdata=6'b000000;
		 gvdata=6'b000000;
		 bvdata=6'b000000;
		 end
	  if(line_counter>=thb+60&&line_counter<thb+120)//red
	    begin
	   rvdata=6'b111111;
		 gvdata=6'b000000;
		 bvdata=6'b000000;
		 end
	 if(line_counter>=thb+120&&line_counter<thb+180)//yellow
	    begin
	   rvdata=6'b111111;
		 gvdata=6'b111111;
		 bvdata=6'b000000;
		 end
		    if(line_counter>=thb+180&&line_counter<thb+240)//green
	    begin
	   rvdata=6'b000000;
		 gvdata=6'b111111;
		 bvdata=6'b000000;
		 end
	  if(line_counter>=thb+240&&line_counter<thb+300)//cyan
	    begin
	    rvdata=6'b000000;
		 gvdata=6'b111111;
		 bvdata=6'b111111;
		 end
	 if(line_counter>=thb+300&&line_counter<thb+360)//blue
	    begin
	    rvdata=6'b000000;
		 gvdata=6'b000000;
		 bvdata=6'b111111;
		 end
	   if(line_counter>=thb+360&&line_counter<thb+420)//magenta
	    begin
	    rvdata=6'b111111;
		 gvdata=6'b000000;
		 bvdata=6'b111111;
		 end
	  if(line_counter>=thb+420&&line_counter<thb+480)//white
	    begin
	    rvdata=6'b111111;
		 gvdata=6'b111111;
		 bvdata=6'b111111;
		 end

end
//*********************dot flicker*******************************
always@(posedge dclk_reg)
begin
    if(line_counter%2==1)
	     if((dot_counter%2)==1)
		    begin
		    frdata=6'b111111;
		    fgdata=6'b000000;
		    fbdata=6'b111111;
		    end
		  else
		    begin
		    frdata=6'b000000;
		    fgdata=6'b111111;
		    fbdata=6'b000000;
		    end
	else
	   if((dot_counter%2)==1)
		  begin
		  frdata=6'b000000;
		  fgdata=6'b111111;
		  fbdata=6'b000000;
		  end
		else
		  begin
		  frdata=6'b111111;
		  fgdata=6'b000000;
		  fbdata=6'b111111;
		  end
end

//******************************vertical gray 64****************************
always@(posedge dclk_reg)
begin
if(dot_counter>=tvb&&dot_counter<tvb+384)//tvb=23
		begin
			if(n==11)	
				begin
					n=0;
					vgray=vgray+1;
				end
			else	n=n+1;
		end
	else if(dot_counter>=tvb+384&&dot_counter<tvb+800)	
			begin
				if(n==12)	
					begin
					n=0;
					vgray=vgray+1;
					end
				else	n=n+1;
			end
	else 
		begin
			vgray=0;
			n=0;
		end
end

//****************************horizontal gray 64****************************
always@(negedge lcd_de)
begin
 		if(line_counter>=thb&&line_counter<thb+224)//thb=46
		begin
			if(v==6)	
				begin
					v=0;
					hgray=hgray+1;
				end
			else	v=v+1;
		end
	else if(line_counter>=thb+224&&line_counter<thb+480)	
			begin
				if(m_counter==7)
					begin
					m_counter=0;
					hgray=hgray+1;
					end
				else	m_counter=m_counter+1;
			end
	else 
		begin
			hgray=0;
			v=0;
			m_counter=0;
		end	
		
end

//****************************chess board****************************
always@(posedge dclk_reg)
begin
     if(dot_counter>=tvb&&dot_counter<tvb+100||dot_counter>=tvb+200&&dot_counter<tvb+300||dot_counter>=tvb+400&&dot_counter<tvb+500||dot_counter>=tvb+600&&dot_counter<tvb+700)
        if(line_counter>=thb&&line_counter<thb+80||line_counter>=thb+160&&line_counter<thb+240||line_counter>=thb+320&&line_counter<thb+400)
		     chessdata=6'b000000;
		  else
		     chessdata=6'b111111;
	  else if(dot_counter>=tvb+100&&dot_counter<tvb+200||dot_counter>=tvb+300&&dot_counter<tvb+400||dot_counter>=tvb+500&&dot_counter<tvb+600||dot_counter>=tvb+700&&dot_counter<tvb+800)
        if(line_counter>=thb&&line_counter<thb+80||line_counter>=thb+160&&line_counter<thb+240||line_counter>=thb+320&&line_counter<thb+400)
		     chessdata=6'b111111;
		  else
		     chessdata=6'b000000;
end

//****************************cross talk****************************
always@(posedge lcd_dclk)
begin
    if(line_counter>=thb+160&&line_counter<thb+320)
	    if(dot_counter>=tvb+266&&dot_counter<tvb+534)
	    crossdata=6'b000000;
	    else
	    crossdata=6'b101110;
	 else
    crossdata=6'b101110;
end

//****************************touch panel the first test************************
always@(posedge lcd_dclk)
begin
    if(line_counter>=thb+20&&line_counter<thb+50)
	    if(dot_counter>=tvb+30&&dot_counter<tvb+70)
	    tp_one=6'b000000;
	    else
	    tp_one=6'b111111;
	 else
    tp_one=6'b111111;
end
//****************************touch panel the second test**********************
always@(posedge lcd_dclk)
begin
    if(line_counter>=thb+430&&line_counter<thb+460)
	    if(dot_counter>=tvb+30&&dot_counter<tvb+70)
	    tp_two=6'b000000;
	    else
	    tp_two=6'b111111;
	 else
    tp_two=6'b111111;
end
//****************************touch panel the third test************************
always@(posedge lcd_dclk)
begin
    if(line_counter>=thb+430&&line_counter<thb+460)
	    if(dot_counter>=tvb+730&&dot_counter<tvb+770)
	    tp_three=6'b000000;
	    else
	    tp_three=6'b111111;
	 else
    tp_three=6'b111111;
end
//****************************touch panel the fourth test***********************
always@(posedge lcd_dclk)
begin
    if(line_counter>=thb+20&&line_counter<thb+50)
	    if(dot_counter>=tvb+730&&dot_counter<tvb+770)
	    tp_four=6'b000000;
	    else
	    tp_four=6'b111111;
	 else
    tp_four=6'b111111;
end
//****************************touch panel the fifth test***********************
always@(posedge lcd_dclk)
begin
    if(line_counter>=thb+225&&line_counter<thb+255)
	    if(dot_counter>=tvb+380&&dot_counter<tvb+420)
	    tp_five=6'b000000;
	    else
	    tp_five=6'b111111;
	 else
    tp_five=6'b111111;
end
//**********************Output pattern****************************
always@(posedge lcd_dclk)
begin
	case(pattern_num)
	
	      0:	begin       //white
					r_out=6'b111111;
					g_out=6'b111111;
					b_out=6'b111111;
					fpga_led0=1;
               fpga_led1=1;
               fpga_led2=0;					
				end
			1:	begin	       //red
					r_out=6'b111111;
					g_out=6'b000000;
					b_out=6'b000000;
					fpga_led0=1;
               fpga_led1=0;
               fpga_led2=1;
				end
			2:	begin      //green
					r_out=6'b000000;
					g_out=6'b111111;
					b_out=6'b000000;
					fpga_led0=0;
               fpga_led1=1;
               fpga_led2=1;					
				end
			3:	begin       //blue
					r_out=6'b000000;
					g_out=6'b000000;
					b_out=6'b111111;
					fpga_led0=1;
               fpga_led1=1;
               fpga_led2=1;
				end
			4:	begin       //black
					r_out=6'b000000;
					g_out=6'b000000;
					b_out=6'b000000;
					fpga_led0=0;
               fpga_led1=0;
               fpga_led2=0;					
				end//white
			5:	begin       //white
					r_out=6'b111111;
					g_out=6'b111111;
					b_out=6'b111111;
					fpga_led0=1;
               fpga_led1=0;
               fpga_led2=0;					
				end
			6:	begin       //half gray
					r_out=6'b101110;
					g_out=6'b101110;
					b_out=6'b101110;
					fpga_led0=0;
               fpga_led1=1;
               fpga_led2=0;					
				end
			7:	begin       //cross talk 
					r_out=crossdata;
					g_out=crossdata;
					b_out=crossdata;
					fpga_led0=1;
               fpga_led1=1;
               fpga_led2=0;					
				end
			8:	begin      //flicker
					r_out=frdata;
					g_out=fgdata;
					b_out=fbdata;
					fpga_led0=1;
               fpga_led1=1;
               fpga_led2=0;					
				end
	      9:	begin     //horizontal color bar
					r_out=rdata;
					g_out=gdata;
					b_out=bdata;
					fpga_led0=1;
               fpga_led1=1;
               fpga_led2=0;					
				end
		   10:	begin    //vertical color bar
					r_out=rvdata;
					g_out=gvdata;
					b_out=bvdata;
					fpga_led0=1;
               fpga_led1=1;
               fpga_led2=0;					
				end	
			11:	begin     //horizontal gray
					r_out=hgray;
					g_out=hgray;
					b_out=hgray;
					fpga_led0=1;
               fpga_led1=1;
               fpga_led2=0;					
				end
			12:	begin      //vertical gray
					r_out=vgray;
					g_out=vgray;
					b_out=vgray;
					fpga_led0=1;
               fpga_led1=1;
               fpga_led2=0;					
				end
			13:	begin      //chess board
					r_out=chessdata;
					g_out=chessdata;
					b_out=chessdata;
               fpga_led0=1;
               fpga_led1=1;
               fpga_led2=0;	
				end
			14:   begin      //touch panel the first test

          r_out=tp_one;
					g_out=tp_one;
					b_out=tp_one;
					
            end			
			
	endcase
end
//**************************
always@(posedge clk)
begin
  if(on_off==1)
		begin		
		lcd_dclk=dclk;
     	lcd_de=de_reg;
		lcd_hs=hs_reg;
		lcd_vs=vs_reg;
		end
	else
		begin
		lcd_dclk=0;
 		lcd_de=0;
		lcd_hs=0;
		lcd_vs=0;
		end
end
//****************************
endmodule