pci_bridge32.tlg

这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序

Selecting top level module pci_bridge32
Synthesizing module pci_out_reg
Synthesizing module pci_rst_int
@W: CL159 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_rst_int.v":91:6:91:10|Input rst_i is unused
@W: CL159 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_rst_int.v":100:6:100:17|Input pci_intan_in is unused
Synthesizing module pci_async_reset_flop
Synthesizing module pci_wb_slave
@N: CL201 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":329:0:329:5|Trying to extract state machine for register c_state
Extracted state machine for register c_state
State machine has 6 reachable states with original encodings of:
   000
   011
   100
   101
   110
   111
@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":193:12:193:20|Input port bit <3> of del_bc_in[3:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":193:12:193:20|Input port bit <2> of del_bc_in[3:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":193:12:193:20|Input port bit <1> of del_bc_in[3:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":193:12:193:20|Input port bit <0> of del_bc_in[3:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":213:14:213:25|Input port bit <31> of ccyc_addr_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":213:14:213:25|Input port bit <30> of ccyc_addr_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":213:14:213:25|Input port bit <29> of ccyc_addr_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":213:14:213:25|Input port bit <28> of ccyc_addr_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":213:14:213:25|Input port bit <27> of ccyc_addr_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":213:14:213:25|Input port bit <26> of ccyc_addr_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":213:14:213:25|Input port bit <25> of ccyc_addr_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":213:14:213:25|Input port bit <24> of ccyc_addr_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":213:14:213:25|Input port bit <23> of ccyc_addr_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":213:14:213:25|Input port bit <22> of ccyc_addr_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":213:14:213:25|Input port bit <21> of ccyc_addr_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":213:14:213:25|Input port bit <20> of ccyc_addr_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":213:14:213:25|Input port bit <19> of ccyc_addr_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":213:14:213:25|Input port bit <18> of ccyc_addr_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":213:14:213:25|Input port bit <17> of ccyc_addr_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":213:14:213:25|Input port bit <16> of ccyc_addr_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":213:14:213:25|Input port bit <15> of ccyc_addr_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":213:14:213:25|Input port bit <14> of ccyc_addr_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":213:14:213:25|Input port bit <13> of ccyc_addr_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":213:14:213:25|Input port bit <12> of ccyc_addr_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":213:14:213:25|Input port bit <11> of ccyc_addr_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":213:14:213:25|Input port bit <10> of ccyc_addr_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":213:14:213:25|Input port bit <9> of ccyc_addr_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":213:14:213:25|Input port bit <8> of ccyc_addr_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":213:14:213:25|Input port bit <7> of ccyc_addr_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":213:14:213:25|Input port bit <6> of ccyc_addr_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":213:14:213:25|Input port bit <5> of ccyc_addr_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":213:14:213:25|Input port bit <4> of ccyc_addr_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":213:14:213:25|Input port bit <3> of ccyc_addr_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":213:14:213:25|Input port bit <2> of ccyc_addr_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":213:14:213:25|Input port bit <1> of ccyc_addr_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":213:14:213:25|Input port bit <0> of ccyc_addr_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":228:16:228:30|Input port bit <31> of wb_conf_data_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":228:16:228:30|Input port bit <30> of wb_conf_data_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":228:16:228:30|Input port bit <29> of wb_conf_data_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":228:16:228:30|Input port bit <28> of wb_conf_data_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":228:16:228:30|Input port bit <27> of wb_conf_data_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":228:16:228:30|Input port bit <26> of wb_conf_data_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":228:16:228:30|Input port bit <25> of wb_conf_data_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":228:16:228:30|Input port bit <24> of wb_conf_data_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":228:16:228:30|Input port bit <23> of wb_conf_data_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":228:16:228:30|Input port bit <22> of wb_conf_data_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":228:16:228:30|Input port bit <21> of wb_conf_data_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":228:16:228:30|Input port bit <20> of wb_conf_data_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":228:16:228:30|Input port bit <19> of wb_conf_data_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":228:16:228:30|Input port bit <18> of wb_conf_data_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":228:16:228:30|Input port bit <17> of wb_conf_data_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":228:16:228:30|Input port bit <16> of wb_conf_data_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":228:16:228:30|Input port bit <15> of wb_conf_data_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":228:16:228:30|Input port bit <14> of wb_conf_data_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":228:16:228:30|Input port bit <13> of wb_conf_data_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":228:16:228:30|Input port bit <12> of wb_conf_data_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":228:16:228:30|Input port bit <11> of wb_conf_data_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":228:16:228:30|Input port bit <10> of wb_conf_data_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":228:16:228:30|Input port bit <9> of wb_conf_data_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":228:16:228:30|Input port bit <8> of wb_conf_data_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":228:16:228:30|Input port bit <7> of wb_conf_data_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":228:16:228:30|Input port bit <6> of wb_conf_data_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":228:16:228:30|Input port bit <5> of wb_conf_data_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":228:16:228:30|Input port bit <4> of wb_conf_data_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":228:16:228:30|Input port bit <3> of wb_conf_data_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":228:16:228:30|Input port bit <2> of wb_conf_data_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":228:16:228:30|Input port bit <1> of wb_conf_data_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":228:16:228:30|Input port bit <0> of wb_conf_data_in[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":256:16:256:29|Input port bit <3> of wbr_fifo_be_in[3:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":256:16:256:29|Input port bit <2> of wbr_fifo_be_in[3:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":256:16:256:29|Input port bit <1> of wbr_fifo_be_in[3:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":256:16:256:29|Input port bit <0> of wbr_fifo_be_in[3:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":258:16:258:34|Input port bit <3> of wbr_fifo_control_in[3:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":258:16:258:34|Input port bit <2> of wbr_fifo_control_in[3:0] is unused

@W: CL159 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":193:12:193:20|Input del_bc_in is unused
@W: CL159 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":211:7:211:18|Input del_error_in is unused
@W: CL159 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":213:14:213:25|Input ccyc_addr_in is unused
@W: CL159 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":228:16:228:30|Input wb_conf_data_in is unused
@W: CL159 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_slave.v":256:16:256:29|Input wbr_fifo_be_in is unused
Synthesizing module RAMB4_S16_S16
@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6300:16:6300:20|Input port bit <7> of ADDRA[7:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6300:16:6300:20|Input port bit <6> of ADDRA[7:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6300:16:6300:20|Input port bit <5> of ADDRA[7:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6300:16:6300:20|Input port bit <4> of ADDRA[7:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6300:16:6300:20|Input port bit <3> of ADDRA[7:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6300:16:6300:20|Input port bit <2> of ADDRA[7:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6300:16:6300:20|Input port bit <1> of ADDRA[7:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6300:16:6300:20|Input port bit <0> of ADDRA[7:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6301:17:6301:19|Input port bit <15> of DIA[15:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6301:17:6301:19|Input port bit <14> of DIA[15:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6301:17:6301:19|Input port bit <13> of DIA[15:0] is unused