pci_bridge32.tlg

来自「这是用pci-wishbone核和16450串口核在xilinx的fpga上实现」· TLG 代码 · 共 957 行 · 第 1/5 页

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":102:42:102:48|Input port bit <15> of bar2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":102:42:102:48|Input port bit <14> of bar2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":102:42:102:48|Input port bit <13> of bar2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":102:42:102:48|Input port bit <12> of bar2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":102:42:102:48|Input port bit <11> of bar2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":102:42:102:48|Input port bit <10> of bar2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":102:42:102:48|Input port bit <9> of bar2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":102:42:102:48|Input port bit <8> of bar2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":102:42:102:48|Input port bit <7> of bar2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":102:42:102:48|Input port bit <6> of bar2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":102:42:102:48|Input port bit <5> of bar2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":102:42:102:48|Input port bit <4> of bar2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":102:42:102:48|Input port bit <3> of bar2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":102:42:102:48|Input port bit <2> of bar2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":102:42:102:48|Input port bit <1> of bar2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":102:42:102:48|Input port bit <0> of bar2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":103:42:103:48|Input port bit <19> of bar3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":103:42:103:48|Input port bit <18> of bar3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":103:42:103:48|Input port bit <17> of bar3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":103:42:103:48|Input port bit <16> of bar3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":103:42:103:48|Input port bit <15> of bar3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":103:42:103:48|Input port bit <14> of bar3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":103:42:103:48|Input port bit <13> of bar3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":103:42:103:48|Input port bit <12> of bar3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":103:42:103:48|Input port bit <11> of bar3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":103:42:103:48|Input port bit <10> of bar3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":103:42:103:48|Input port bit <9> of bar3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":103:42:103:48|Input port bit <8> of bar3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":103:42:103:48|Input port bit <7> of bar3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":103:42:103:48|Input port bit <6> of bar3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":103:42:103:48|Input port bit <5> of bar3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":103:42:103:48|Input port bit <4> of bar3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":103:42:103:48|Input port bit <3> of bar3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":103:42:103:48|Input port bit <2> of bar3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":103:42:103:48|Input port bit <1> of bar3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":103:42:103:48|Input port bit <0> of bar3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":104:42:104:48|Input port bit <19> of bar4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":104:42:104:48|Input port bit <18> of bar4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":104:42:104:48|Input port bit <17> of bar4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":104:42:104:48|Input port bit <16> of bar4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":104:42:104:48|Input port bit <15> of bar4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":104:42:104:48|Input port bit <14> of bar4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":104:42:104:48|Input port bit <13> of bar4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":104:42:104:48|Input port bit <12> of bar4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":104:42:104:48|Input port bit <11> of bar4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":104:42:104:48|Input port bit <10> of bar4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":104:42:104:48|Input port bit <9> of bar4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":104:42:104:48|Input port bit <8> of bar4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":104:42:104:48|Input port bit <7> of bar4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":104:42:104:48|Input port bit <6> of bar4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":104:42:104:48|Input port bit <5> of bar4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":104:42:104:48|Input port bit <4> of bar4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":104:42:104:48|Input port bit <3> of bar4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":104:42:104:48|Input port bit <2> of bar4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":104:42:104:48|Input port bit <1> of bar4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":104:42:104:48|Input port bit <0> of bar4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":105:42:105:48|Input port bit <19> of bar5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":105:42:105:48|Input port bit <18> of bar5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":105:42:105:48|Input port bit <17> of bar5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":105:42:105:48|Input port bit <16> of bar5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":105:42:105:48|Input port bit <15> of bar5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":105:42:105:48|Input port bit <14> of bar5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":105:42:105:48|Input port bit <13> of bar5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":105:42:105:48|Input port bit <12> of bar5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":105:42:105:48|Input port bit <11> of bar5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":105:42:105:48|Input port bit <10> of bar5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":105:42:105:48|Input port bit <9> of bar5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":105:42:105:48|Input port bit <8> of bar5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":105:42:105:48|Input port bit <7> of bar5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":105:42:105:48|Input port bit <6> of bar5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":105:42:105:48|Input port bit <5> of bar5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":105:42:105:48|Input port bit <4> of bar5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":105:42:105:48|Input port bit <3> of bar5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":105:42:105:48|Input port bit <2> of bar5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":105:42:105:48|Input port bit <1> of bar5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":105:42:105:48|Input port bit <0> of bar5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":106:42:106:47|Input port bit <19> of am0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":106:42:106:47|Input port bit <18> of am0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":106:42:106:47|Input port bit <17> of am0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":106:42:106:47|Input port bit <16> of am0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":106:42:106:47|Input port bit <15> of am0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":106:42:106:47|Input port bit <14> of am0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":106:42:106:47|Input port bit <13> of am0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":106:42:106:47|Input port bit <12> of am0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":106:42:106:47|Input port bit <11> of am0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":106:42:106:47|Input port bit <10> of am0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":106:42:106:47|Input port bit <9> of am0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":106:42:106:47|Input port bit <8> of am0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":106:42:106:47|Input port bit <7> of am0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":106:42:106:47|Input port bit <6> of am0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":106:42:106:47|Input port bit <5> of am0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":106:42:106:47|Input port bit <4> of am0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":106:42:106:47|Input port bit <3> of am0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":106:42:106:47|Input port bit <2> of am0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":106:42:106:47|Input port bit <1> of am0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":106:42:106:47|Input port bit <0> of am0_in[19:0] is unused