coregen.log

来自「this program performs the functonality o」· LOG 代码 · 共 22 行

# Xilinx CORE Generator 6.3i
# User = Administrator
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in G:\vijay_FPGA_LAB\4bit_alu\coregen.log
# busformat=BusFormatAngleBracketNotRipped
# designflow=VHDL
# expandedprojectpath=G:\vijay_FPGA_LAB\4bit_alu
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=VHDL
# xilinxfamily=Virtex2
# outputoption=DesignFlow
# overwritefiles=Default
# simvendor=ModelSim
# expandedprojectpath=G:\vijay_FPGA_LAB\4bit_alu
SETPROJECT .
Set current Project to G:\vijay_FPGA_LAB\4bit_alu
SET BusFormat = BusFormatAngleBracketNotRipped
SETXIPCPORTHOST 1032
XIPCPJSENDCORES spartan3