代码搜索：Annotation
找到约 6,069 项符合「Annotation」的源代码
代码结果 6,069
www.eeworm.com/read/281423/4116428
msg top.msg
@TM:1158617706
@N: :"":0:0:0:-1|Gated clock conversion disabled
@N: BN191 :"":0:0:0:-1|Writing property annotation file C:\Actelprj\PA3_DemoBoard_72\synthesis\TOP.tap.
@N: BN225 :"":0:0:0:-1|Writ
www.eeworm.com/read/419129/2080812
java timeservicebean.java
/**
* Copyright (c)上海烟草(集团)公司与上海康时信息系统有限公司。
*/
package com.myejb.imp;
import java.util.Date;
import javax.annotation.Resource;
import javax.ejb.Remote;
import javax.ejb.SessionContext;
i
www.eeworm.com/read/419129/2080820
java operationbean.java
/**
* Copyright (c)上海烟草(集团)公司与上海康时信息系统有限公司。
*/
package com.myejb.imp;
import javax.ejb.Local;
import javax.ejb.Remote;
import javax.ejb.Stateless;
import org.jboss.annotation.ejb.LocalBin
www.eeworm.com/read/154076/5643171
ant alu_tst_wave.ant
// J:\TEMP\EXAM\HDLBENCHER-ALU\ALU_VLOG
// Verilog Annotation Test Bench created by
// HDL Bencher 5.1i
// Thu Dec 19 17:46:39 2002
`timescale 1ns/1ns
`define op_sub 1
`define op_and 2
`def
www.eeworm.com/read/235010/14088995
ant test_ddr_command.ant
// F:\ISE_TEST
// Verilog Annotation Test Bench created by
// HDL Bencher 6.1i
// Tue Aug 14 10:56:43 2007
`timescale 1ns/1ns
`define FDEPTH 4
`define C_READ 5
`define D 10
`define IF2 3
www.eeworm.com/read/314805/13558913
ant clock-wave.ant
-- E:\资料\计算机设计与实践\MYCPU16
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Sun Nov 11 22:40:14 2007
LIBRARY IEEE;
USE IEEE.STD_LOGIC_ARITH.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONE
www.eeworm.com/read/128604/5982057
entries
/Annotation.java/1.2/Tue Jan 22 22:40:37 2002//Tgcc-3_4-branch
/AttributedCharacterIterator.java/1.5/Wed Oct 15 13:57:00 2003//Tgcc-3_4-branch
/AttributedString.java/1.2/Tue Jan 22 22:40:37 2002//Tgcc
www.eeworm.com/read/430277/6290776
msg uart_test.msg
@TM:1215572020
@N: BN225 :"":0:0:0:-1|Writing default property annotation file E:\Easy FPGA030\UART\synthesis\uart_test.map.
@TM:1215217406
@N: MF249 :"":0:0:0:-1|Running in 32-bit mode.
@TM:12152
www.eeworm.com/read/417857/2098516
seq seqwords.seq
ID ACEA_ECOLI STANDARD; PRT; 434 AA.
AC P05313;
DT 01-NOV-1988 (Rel. 09, Created)
DT 01-NOV-1988 (Rel. 09, Last sequence update)
DT 15-DEC-1998 (Rel. 37, Last annotation update)
D
www.eeworm.com/read/198746/6786452
ant mvbc3tbw.ant
// D:\2006\FPGA_DESIGN\MVBC3\MVBC3
// Verilog Annotation Test Bench created by
// HDL Bencher 6.1i
// Wed Jan 10 21:08:37 2007
`timescale 1ns/1ns
module mvbc3tbw;
reg clk;
reg rst;
reg