mvbc3tbw.ant

MVBC VHDL代码．．实现多功能车辆总线的通信

// D:\2006\FPGA_DESIGN\MVBC3\MVBC3
// Verilog Annotation Test Bench created by
// HDL Bencher 6.1i
// Wed Jan 10 21:08:37 2007

`timescale 1ns/1ns

module mvbc3tbw;
	reg clk;
	reg rst;
	reg cs_cpu_n;
	reg int_mvbc0_n;
	reg int_mvbc1_n;
	reg wr_cpu_n;
	reg oe_cpu_n;
	reg [23:0] addr_cpu;
	reg rdy2mvbc_n;
	reg [6:0] CS;
	wire [23:0] addr_mvbc;
	wire rdy2cpu_n;
	wire rst_mvbc;
	wire wr_mvbc_n;
	wire rd_mvbc_n;
	wire cs_mvbc_n;
	wire int_cpu0_n;
	wire int_cpu1_n;
	wire JTEG_EN;
	wire SPARE0;

	mvbif UUT (
		.clk(clk),
		.rst(rst),
		.cs_cpu_n(cs_cpu_n),
		.int_mvbc0_n(int_mvbc0_n),
		.int_mvbc1_n(int_mvbc1_n),
		.wr_cpu_n(wr_cpu_n),
		.oe_cpu_n(oe_cpu_n),
		.addr_cpu(addr_cpu),
		.rdy2mvbc_n(rdy2mvbc_n),
		.CS(CS),
		.addr_mvbc(addr_mvbc),
		.rdy2cpu_n(rdy2cpu_n),
		.rst_mvbc(rst_mvbc),
		.wr_mvbc_n(wr_mvbc_n),
		.rd_mvbc_n(rd_mvbc_n),
		.cs_mvbc_n(cs_mvbc_n),
		.int_cpu0_n(int_cpu0_n),
		.int_cpu1_n(int_cpu1_n),
		.JTEG_EN(JTEG_EN),
		.SPARE0(SPARE0)
	);

	integer TX_FILE;
	integer TX_ERROR;

always
begin 			//clock process
	clk = 1'b0;
	#5
	clk = 1'b1;
	#5
	ANNOTATE_addr_mvbc;
	ANNOTATE_rdy2cpu_n;
	ANNOTATE_rst_mvbc;
	ANNOTATE_wr_mvbc_n;
	ANNOTATE_rd_mvbc_n;
	ANNOTATE_cs_mvbc_n;
	ANNOTATE_int_cpu0_n;
	ANNOTATE_int_cpu1_n;
	ANNOTATE_JTEG_EN;
	ANNOTATE_SPARE0;
	#5
	clk = 1'b0;
	#5
	clk = 1'b0;
end

initial
begin
	TX_ERROR=0;
	TX_FILE=$fopen("d:\\2006\\fpga_design\\mvbc3\\mvbc3\\mvbc3tbw.ano");

	// --------------------
	rst = 1'b0;
	cs_cpu_n = 1'b1;
	int_mvbc0_n = 1'b0;
	int_mvbc1_n = 1'b0;
	wr_cpu_n = 1'b0;
	oe_cpu_n = 1'b0;
	addr_cpu = 24'b000000000000000000000000; //0
	rdy2mvbc_n = 1'b0;
	CS = 7'b0000000; //0
	// --------------------
	#20 // Time=20 ns
	rst = 1'b1;
	cs_cpu_n = 1'b1;
	// --------------------
	#20 // Time=40 ns
	cs_cpu_n = 1'b1;
	// --------------------
	#20 // Time=60 ns
	cs_cpu_n = 1'b1;
	rdy2mvbc_n = 1'b0;
	// --------------------
	#20 // Time=80 ns
	cs_cpu_n = 1'b0;
	// --------------------
	#60 // Time=140 ns
	cs_cpu_n = 1'b0;
	// --------------------
	#120 // Time=260 ns
	cs_cpu_n = 1'b1;
	// --------------------
	#40 // Time=300 ns
	cs_cpu_n = 1'b1;
	// --------------------
	#20 // Time=320 ns
	rdy2mvbc_n = 1'b0;
	// --------------------
	#60 // Time=380 ns
	rst = 1'b1;
	// --------------------
	#100 // Time=480 ns
	rdy2mvbc_n = 1'b0;
	// --------------------
	#40 // Time=520 ns
	cs_cpu_n = 1'b0;
	// --------------------
	#60 // Time=580 ns
	cs_cpu_n = 1'b1;
	// --------------------
	#140 // Time=720 ns
	rst = 1'b1;
	// --------------------
	#20 // Time=740 ns
	rst = 1'b1;
	// --------------------
	#20 // Time=760 ns
	cs_cpu_n = 1'b0;
	// --------------------
	#420 // Time=1180 ns
	cs_cpu_n = 1'b1;
	// --------------------
	#390 // Time=1570 ns
	// --------------------

	begin
		$display("Success! Annotation Simulation Complete.");
		$fdisplay(TX_FILE,"Total[%d]",TX_ERROR);
	end

	$fclose(TX_FILE);
	$stop;

end

task ANNOTATE_addr_mvbc;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,addr_mvbc,%b]",
			$time, addr_mvbc);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_rdy2cpu_n;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,rdy2cpu_n,%b]",
			$time, rdy2cpu_n);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_rst_mvbc;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,rst_mvbc,%b]",
			$time, rst_mvbc);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_wr_mvbc_n;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,wr_mvbc_n,%b]",
			$time, wr_mvbc_n);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_rd_mvbc_n;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,rd_mvbc_n,%b]",
			$time, rd_mvbc_n);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_cs_mvbc_n;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,cs_mvbc_n,%b]",
			$time, cs_mvbc_n);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_int_cpu0_n;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,int_cpu0_n,%b]",
			$time, int_cpu0_n);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_int_cpu1_n;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,int_cpu1_n,%b]",
			$time, int_cpu1_n);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_JTEG_EN;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,JTEG_EN,%b]",
			$time, JTEG_EN);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

task ANNOTATE_SPARE0;
	#0 begin
		$fdisplay(TX_FILE,"Annotate[%d,SPARE0,%b]",
			$time, SPARE0);
		TX_ERROR = TX_ERROR + 1;
	end
endtask

endmodule