clock-wave.ant

16位cpu设计VHDL源码

-- E:\资料\计算机设计与实践\MYCPU16
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Sun Nov 11 22:40:14 2007

LIBRARY IEEE;
USE IEEE.STD_LOGIC_ARITH.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY clock-wave IS
END clock-wave;

ARCHITECTURE testbench_arch OF clock-wave IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "e:\资料\计算机设计与实践\mycpu16\clock-wave.ano";
	COMPONENT clock
		PORT (
			clk : In  std_logic;
			RST : In  std_logic;
			T : Out  std_logic_vector (4 DOWNTO 0)
		);
	END COMPONENT;

	SIGNAL clk : std_logic;
	SIGNAL RST : std_logic;
	SIGNAL T : std_logic_vector (4 DOWNTO 0);

BEGIN
	UUT : clock
	PORT MAP (
		clk => clk,
		RST => RST,
		T => T
	);

	PROCESS -- clock process for clk,
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_T(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",T,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, T);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CLOCK_LOOP : LOOP
		clk <= transport '0';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		clk <= transport '1';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		ANNOTATE_T(TX_TIME);
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		clk <= transport '0';
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clk
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		RST <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		RST <= transport '1';
		-- --------------------
		WAIT FOR 400 ns; -- Time=500 ns
		RST <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=600 ns
		RST <= transport '1';
		-- --------------------
		WAIT FOR 300 ns; -- Time=900 ns
		RST <= transport '0';
		-- --------------------
		WAIT FOR 210 ns; -- Time=1110 ns
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION clock_cfg OF clock-wave IS
	FOR testbench_arch
	END FOR;
END clock_cfg;