uart_test.msg

主芯片：Actel的FPGA030,Verilog语言,串口发送和接收的例程

@TM:1215572020
@N: BN225 :"":0:0:0:-1|Writing default property annotation file E:\Easy FPGA030\UART\synthesis\uart_test.map.
@TM:1215217406
@N: MF249 :"":0:0:0:-1|Running in 32-bit mode.
@TM:1215217409
@N: MT320 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT322 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock..
@TM:1215572020
@N: CG364 :"E:\Easy FPGA030\UART\hdl\rec.v":5:7:5:9|Synthesizing module rec
@N: MF238 :"e:\easy fpga030\uart\hdl\rec.v":26:7:26:15|M
@W: CL170 :"E:\Easy FPGA030\UART\hdl\rec.v":37:0:37:5|M
@N: MF238 :"e:\easy fpga030\uart\hdl\rec.v":54:11:54:21|M
@N: CG364 :"E:\Easy FPGA030\UART\hdl\send.v":6:7:6:10|Synthesizing module send
@N: MF238 :"e:\easy fpga030\uart\hdl\send.v":35:6:35:14|M
@W: CL171 :"E:\Easy FPGA030\UART\hdl\send.v":42:0:42:5|M
@W: CL189 :"E:\Easy FPGA030\UART\hdl\send.v":42:0:42:5|M
@N:  :"e:\easy fpga030\uart\hdl\send.v":54:0:54:5|M
@W: CL170 :"E:\Easy FPGA030\UART\hdl\send.v":54:0:54:5|M
@N: CG364 :"E:\Easy FPGA030\UART\hdl\uart_test.v":5:7:5:15|Synthesizing module uart_test
@W: CG360 :"E:\Easy FPGA030\UART\hdl\uart_test.v":21:5:21:11|M
@N: MF238 :"e:\easy fpga030\uart\hdl\uart_test.v":36:16:36:28|M