代码搜索：Annotation

找到约 6,069 项符合「Annotation」的源代码

代码结果 6,069
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
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ant testwave.ant

-- D:\MODEL\LAB3 -- VHDL Annotation Test Bench created by -- HDL Bencher 6.1i -- Fri Jun 16 15:52:07 2006 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; USE IEEE.STD_LOGIC_
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www.eeworm.com/read/447996/7542347

ant tst_alu_2bit.ant

-- G:\VIJAY_FPGA_LAB\ALU_2BIT -- VHDL Annotation Test Bench created by -- HDL Bencher 6.1i -- Thu Mar 09 14:22:39 2006 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; US
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www.eeworm.com/read/447996/7542348

ant alu_2bit.ant

-- G:\VIJAY_FPGA_LAB\ALU_2BIT -- VHDL Annotation Test Bench created by -- HDL Bencher 6.1i -- Sat Feb 18 09:35:47 2006 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; US
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www.eeworm.com/read/18421/787145

msg top.msg

@TM:1158617706 @N: :"":0:0:0:-1|Gated clock conversion disabled @N: BN191 :"":0:0:0:-1|Writing property annotation file C:\Actelprj\PA3_DemoBoard_72\synthesis\TOP.tap. @N: BN225 :"":0:0:0:-1|Writ
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www.eeworm.com/read/18563/794271

ant alu_tst_wave.ant

// J:\TEMP\EXAM\HDLBENCHER-ALU\ALU_VLOG // Verilog Annotation Test Bench created by // HDL Bencher 5.1i // Thu Dec 19 17:46:39 2002 `timescale 1ns/1ns `define op_sub 1 `define op_and 2 `def
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www.eeworm.com/read/18679/799744

msg top.msg

@TM:1158617706 @N: :"":0:0:0:-1|Gated clock conversion disabled @N: BN191 :"":0:0:0:-1|Writing property annotation file C:\Actelprj\PA3_DemoBoard_72\synthesis\TOP.tap. @N: BN225 :"":0:0:0:-1|Writ
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www.eeworm.com/read/38039/1091575

mnu reftype.mnu

REF#TYPE 参考类型 # remove the # sign and enter foreign help string in this line By#edge 边 Select annotation plane, and two edge references for reference dimension. 选取用作参照尺寸的注释平面及两条边参照。 By#surf 根据曲面 Sele
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www.eeworm.com/read/231081/4717944

msg top.msg

@TM:1158617706 @N: :"":0:0:0:-1|Gated clock conversion disabled @N: BN191 :"":0:0:0:-1|Writing property annotation file C:\Actelprj\PA3_DemoBoard_72\synthesis\TOP.tap. @N: BN225 :"":0:0:0:-1|Writ
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www.eeworm.com/read/343627/3218952

ant alu_tst_wave.ant

// J:\TEMP\EXAM\HDLBENCHER-ALU\ALU_VLOG // Verilog Annotation Test Bench created by // HDL Bencher 5.1i // Thu Dec 19 17:46:39 2002 `timescale 1ns/1ns `define op_sub 1 `define op_and 2 `def
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www.eeworm.com/read/303381/3813895

msg mc8051_core_struc.msg

@TM:1178208288 @N: :"":0:0:0:-1|Writing default property annotation file D:\CNU\Paper\mc8051_design\synpl\rev_1\mc8051_core_struc.map. @TM:1178208287 @N: FX164 :"":0:0:0:-1|The option to pack flop
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