alu_2bit.ant

this programs gives the functionality of 2bit alu

-- G:\VIJAY_FPGA_LAB\ALU_2BIT
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Sat Feb 18 09:35:47 2006

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY alu_2bit IS
END alu_2bit;

ARCHITECTURE testbench_arch OF alu_2bit IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "g:\vijay_fpga_lab\alu_2bit\alu_2bit.ano";
	COMPONENT alu_2bit
		PORT (
			dis_out : Out  std_logic_vector (7 DOWNTO 0);
			ain : In  std_logic_vector (1 DOWNTO 0);
			bin : In  std_logic_vector (1 DOWNTO 0);
			sout : Out  std_logic_vector (1 DOWNTO 0);
			sel : In  std_logic;
			m : In  std_logic;
			clk1 : In  std_logic;
			cin : In  std_logic;
			cout : Out  std_logic;
			oen1 : Out  std_logic;
			ce : In  std_logic;
			oen2 : Out  std_logic;
			oen3 : Out  std_logic;
			oen4 : Out  std_logic
		);
	END COMPONENT;

	SIGNAL dis_out : std_logic_vector (7 DOWNTO 0);
	SIGNAL ain : std_logic_vector (1 DOWNTO 0);
	SIGNAL bin : std_logic_vector (1 DOWNTO 0);
	SIGNAL sout : std_logic_vector (1 DOWNTO 0);
	SIGNAL sel : std_logic;
	SIGNAL m : std_logic;
	SIGNAL clk1 : std_logic;
	SIGNAL cin : std_logic;
	SIGNAL cout : std_logic;
	SIGNAL oen1 : std_logic;
	SIGNAL ce : std_logic;
	SIGNAL oen2 : std_logic;
	SIGNAL oen3 : std_logic;
	SIGNAL oen4 : std_logic;

BEGIN
	UUT : alu_2bit
	PORT MAP (
		dis_out => dis_out,
		ain => ain,
		bin => bin,
		sout => sout,
		sel => sel,
		m => m,
		clk1 => clk1,
		cin => cin,
		cout => cout,
		oen1 => oen1,
		ce => ce,
		oen2 => oen2,
		oen3 => oen3,
		oen4 => oen4
	);

	PROCESS -- clock process for clk1,
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_dis_out(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",dis_out,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, dis_out);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_sout(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",sout,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, sout);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_cout(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",cout,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, cout);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_oen1(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",oen1,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, oen1);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_oen2(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",oen2,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, oen2);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_oen3(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",oen3,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, oen3);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_oen4(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",oen4,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, oen4);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CLOCK_LOOP : LOOP
		clk1 <= transport '0';
		WAIT FOR 20 us;
		TX_TIME := TX_TIME + 20;
		clk1 <= transport '1';
		WAIT FOR 20 us;
		TX_TIME := TX_TIME + 20;
		ANNOTATE_dis_out(TX_TIME);
		ANNOTATE_sout(TX_TIME);
		ANNOTATE_cout(TX_TIME);
		ANNOTATE_oen1(TX_TIME);
		ANNOTATE_oen2(TX_TIME);
		ANNOTATE_oen3(TX_TIME);
		ANNOTATE_oen4(TX_TIME);
		WAIT FOR 80 us;
		TX_TIME := TX_TIME + 80;
		clk1 <= transport '0';
		WAIT FOR 80 us;
		TX_TIME := TX_TIME + 80;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clk1
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		ain <= transport std_logic_vector'("00"); --0
		bin <= transport std_logic_vector'("00"); --0
		sel <= transport '0';
		m <= transport '0';
		cin <= transport '0';
		ce <= transport '0';
		-- --------------------
		WAIT FOR 200 us; -- Time=200 us
		ain <= transport std_logic_vector'("01"); --1
		bin <= transport std_logic_vector'("01"); --1
		m <= transport '1';
		-- --------------------
		WAIT FOR 200 us; -- Time=400 us
		ain <= transport std_logic_vector'("00"); --0
		bin <= transport std_logic_vector'("01"); --1
		-- --------------------
		WAIT FOR 200 us; -- Time=600 us
		ain <= transport std_logic_vector'("01"); --1
		bin <= transport std_logic_vector'("00"); --0
		-- --------------------
		WAIT FOR 200 us; -- Time=800 us
		m <= transport '0';
		-- --------------------
		WAIT FOR 320 us; -- Time=1120 us
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION alu_2bit_cfg OF alu_2bit IS
	FOR testbench_arch
	END FOR;
END alu_2bit_cfg;