testwave.ant

来自「一个简单的探测110三位的探测器」· ANT 代码 · 共 121 行

-- D:\MODEL\LAB3
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Fri Jun 16 15:52:07 2006

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY testwave IS
END testwave;

ARCHITECTURE testbench_arch OF testwave IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "d:\model\lab3\testwave.ano";
	COMPONENT detector
		PORT (
			A : In  std_logic;
			XLXN_50 : In  std_logic;
			Y : Out  std_logic
		);
	END COMPONENT;

	SIGNAL A : std_logic;
	SIGNAL XLXN_50 : std_logic;
	SIGNAL Y : std_logic;

BEGIN
	UUT : detector
	PORT MAP (
		A => A,
		XLXN_50 => XLXN_50,
		Y => Y
	);

	PROCESS -- clock process for XLXN_50,
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_Y(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",Y,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Y);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CLOCK_LOOP : LOOP
		XLXN_50 <= transport '0';
		WAIT FOR 5 ns;
		TX_TIME := TX_TIME + 5;
		XLXN_50 <= transport '1';
		WAIT FOR 5 ns;
		TX_TIME := TX_TIME + 5;
		ANNOTATE_Y(TX_TIME);
		WAIT FOR 5 ns;
		TX_TIME := TX_TIME + 5;
		XLXN_50 <= transport '0';
		WAIT FOR 5 ns;
		TX_TIME := TX_TIME + 5;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for XLXN_50
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		A <= transport '0';
		-- --------------------
		WAIT FOR 20 ns; -- Time=20 ns
		A <= transport '1';
		-- --------------------
		WAIT FOR 40 ns; -- Time=60 ns
		A <= transport '0';
		-- --------------------
		WAIT FOR 20 ns; -- Time=80 ns
		A <= transport '1';
		-- --------------------
		WAIT FOR 20 ns; -- Time=100 ns
		A <= transport '0';
		-- --------------------
		WAIT FOR 20 ns; -- Time=120 ns
		A <= transport '1';
		-- --------------------
		WAIT FOR 60 ns; -- Time=180 ns
		A <= transport '0';
		-- --------------------
		WAIT FOR 20 ns; -- Time=200 ns
		A <= transport '1';
		-- --------------------
		WAIT FOR 40 ns; -- Time=240 ns
		A <= transport '0';
		-- --------------------
		WAIT FOR 65 ns; -- Time=305 ns
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION detector_cfg OF testwave IS
	FOR testbench_arch
	END FOR;
END detector_cfg;