代码搜索：1KHZ
找到约 286 项符合「1KHZ」的源代码
代码结果 286
www.eeworm.com/read/322256/7083260
m rls_rf3.m
clc;clear all;close all;
% 纯净信号为数字调幅信号8ASK，载频100KHz,波特率1KHz,采样率600K
x = dmod([0,3,1,3,2,0],100e3,1e3,600e3,'ask',8)';
N = length(x);
%-------------------不随机产生的相关噪声---------------------------------
www.eeworm.com/read/453076/7427474
c sp.c
#include "msp430x16x.h"
//输出1KHz方波音频信号
void Init_Port() {
P4DIR=BIT3+BIT2; //SP引脚分配
P4OUT=BIT3;
}
void Init_Clock() {
unsigned char i;
BCSCTL1=0x00;//XT2--ON
do {
IFG1&=~OF
www.eeworm.com/read/17522/737272
v time_disp_select.v
module time_disp_select(
clk_1khz,//1kHz时钟信号输入，用于动态显示时间
clk_200hz,//200Hz时钟信号输入，用于闪烁显示时间
Time_EN,//时间自动工作模式使能
TimeSet_EN,//时间设置使能
timeset_disp_drive,//时间设置数据显示的同步信号
www.eeworm.com/read/18055/772218
v fdiv.v
module fdiv(
clk,
f200hz,
f60hz,
f1hz
);
output f200hz,f60hz,f1hz;
input clk; //1KHz input
reg f200hz,f60hz,f1hz;
integer CNT1=0,CNT2=0,CNT3=0;
always @(posedge clk)
be
www.eeworm.com/read/18055/772707
v fdiv.v
module fdiv(
clk,
f200hz,
f60hz,
f1hz
);
output f200hz,f60hz,f1hz;
input clk; //1KHz input
reg f200hz,f60hz,f1hz;
integer CNT1=0,CNT2=0,CNT3=0;
always @(posedge clk)
be
www.eeworm.com/read/185953/8970473
c 06_7_12_23_30_main.c
/*
*Author hejun
*Date 2006_7_12
*/
/*
*按键功能说明
P1_5 设置步进 100Hz 1KHz 10KHz 100KHz 1MHz 10Mhz
P1_6 步进加1
P1_7 步进减1
*
*/
/*SystemClock=180MHz*/
//F_out=10MHz FrqDWord=238609294; W1=0x
www.eeworm.com/read/185953/8970508
c 06_7_12_12_30_main.c
/*
*Author hejun
*Date 2006_7_12
*/
/*
*按键功能说明
P1_5 设置步进 100Hz 1KHz 10KHz 100KHz 1MHz 10Mhz
P1_6 步进加1
P1_7 步进减1
*
*/
/*SystemClock=180MHz*/
//F_out=10MHz FrqDWord=238609294; W1=0x
www.eeworm.com/read/280649/10300490
cir ex2_20.cir
Ex2_20.CIR - Zener diode spike clipper
.PARAM f=1kHz T={1/f}
vs 1 0 SIN( 0V 10V {f} )
* Set 10V spike at positive peak of vs
vp 2 1 PULSE( 0V 10V {T/4} {T/100} {T/100} 1us {T} )
R 2 3 1ohm
D1 4
www.eeworm.com/read/467468/7003801
v fengping1_500.v
module fengping1_500(clk,f1,f500);
input clk;//输入1khz
output f1,f500;//输出f1 1hz,f2 500hz
wire clk;
reg f1,f500;
//内部寄存器
reg [9:0] count1;
reg count2;
always @(posedge clk)
begin
i
www.eeworm.com/read/301054/13867040
ucf stopwatch.ucf
net led_clk loc = p80; #1KHZ
net led_rst loc = p57;
net pause loc = p59;
net led_sel loc = p3;
net led_sel loc = p5;
net led_sel loc = p7;
net led_sel loc = p9;
net led_seg