fengping1_500.v

来自「在FPGA上」· Verilog 代码 · 共 51 行

module fengping1_500(clk,f1,f500);

input  clk;//输入1khz
output  f1,f500;//输出f1 1hz,f2 500hz

wire clk;
reg f1,f500;
//内部寄存器
reg [9:0] count1;
reg   count2;

always @(posedge clk)
begin
	if(count1==999)
	begin
		count1<=0;
		f1<=1;
	end
	else if(count1<999)
	begin
		count1<=count1+1;
		f1<=0;
	end
	else
	begin
		count1<=0;
		f1<=0;
	end
end

always @(posedge clk)
begin
	if(count2==1)
	begin
		count2<=0;
		f500<=1;
	end
	else if(count2<1)
	begin
		count2<=count2+1;
		f500<=0;
	end
	else
	begin
		count2<=0;
		f500<=0;
	end
end

endmodule