stopwatch.ucf

一套基于XILIX,SPATAN2,XC2S200 芯片实验板上的,10个典型VRILOGHDL的FPGA实验,有帮助,

net led_clk loc = p80;	#1KHZ
net led_rst loc = p57;
net pause   loc = p59;

net led_sel<3> loc = p3;
net led_sel<2> loc = p5;
net led_sel<1> loc = p7;
net led_sel<0> loc = p9;

net led_seg<7> loc = p14;
net led_seg<6> loc = p16;
net led_seg<5> loc = p18;
net led_seg<4> loc = p21;
net led_seg<3> loc = p23;
net led_seg<2> loc = p27;
net led_seg<1> loc = p30;
net led_seg<0> loc = p33;