sig_gen.v

来自「一套基于XILIX,SPATAN2,XC2S200 芯片实验板上的,10个典型V」· Verilog 代码 · 共 53 行

module sig_gen(sysclk, rst_n, mode, data, CS, WR);
	input sysclk, rst_n;
	input wire[1:0] mode;
	output wire[7:0] data;
	output reg CS, WR;

	reg [7:0] counter;
	reg addsub;

	always @(posedge sysclk or negedge rst_n)
	begin
		if (!rst_n)
		begin
			counter = 0;
			addsub = 0;
			CS = 0;
			WR = 0;
		end
		else
		begin
			case (mode)
				2'b00 : counter = counter + 1;	//递增斜波
				2'b01 : counter = counter - 1;	//递减斜波
				2'b10 :	// 三角波
				begin
					if (addsub == 0)
					begin
						counter = counter + 1;
						if (counter == 254)
							addsub = 1;
						else
							addsub = 0;
					end
					else
					begin
						counter = counter - 1;
						if (counter < 1)
							addsub = 0;
						else
							addsub = 1;
					end
				end
				2'b11 : counter = counter + 32;	//递增阶梯波
				default : counter = 0;
			endcase
		end

	end

	assign data = counter;

endmodule