代码搜索：1KHZ
找到约 286 项符合「1KHZ」的源代码
代码结果 286
www.eeworm.com/read/161666/10388074
vhd display.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY display IS
PORT( sclk: IN STD_LOGIC; --scan frequency,about 1KHZ
r
www.eeworm.com/read/464438/7158536
vhd lcd_driver.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lcd is
Port ( clk : in std_logic; --1khz的扫描频率；
reset : in s
www.eeworm.com/read/391317/8409515
vhd traffic_lights.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity traffic_lights is
port(clk: in std_logic;------1khz;
stop:in std_logic;
adr:out std_logic_vector(1
www.eeworm.com/read/353029/10477658
vhd clock_1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock_1 is
port(clk:in std_logic;----时钟输入 1khz
clr:in std_logic;----清零
en:in std_logic;-----暂停
www.eeworm.com/read/461613/7223262
bak lcd.c.bak
#include "globals.h"
#include "EcosLogo.c"
/* Beep Routines
Buzzer PORTX, bitY
10,5 //1kHz per secund
5,5 //2kHz
7,5 //1428 Hz for .56 sec
6,5
Anton Ivanov '02
*/
www.eeworm.com/read/461613/7223289
c lcd.c
#include "globals.h"
#include "EcosLogo.c"
/* Beep Routines
Buzzer PORTX, bitY
10,5 //1kHz per secund
5,5 //2kHz
7,5 //1428 Hz for .56 sec
6,5
Anton Ivanov '02
*/
www.eeworm.com/read/336234/12462471
m sigmix_2ch.m
function [S,A,X,Fs] = Sigmix_2ch
% Sigmix_2ch is used to generate a mixture of 2 sine signals at
% 1kHz and 2kHz with 30800 sample at sampling rate of 16kHz
% Usage: [S,A,X,Fs] = Sigmix_2ch
% Inpu
www.eeworm.com/read/17631/746389
vhd clock_1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock_1 is
port(clk:in std_logic;----时钟输入 1khz
clr:in std_logic;----清零
en:in std_logic;-----暂停
www.eeworm.com/read/32279/881937
vhd clock_1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock_1 is
port(clk:in std_logic;----时钟输入 1khz
clr:in std_logic;----清零
en:in std_logic;-----暂停
www.eeworm.com/read/39267/1124955
vhd clock_1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock_1 is
port(clk:in std_logic;----时钟输入 1khz
clr:in std_logic;----清零
en:in std_logic;-----暂停