📄 display.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY display IS
PORT( sclk: IN STD_LOGIC; --scan frequency,about 1KHZ
reset: IN STD_LOGIC;
trandis: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--8bits for LED display
disselect: OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
--adress line for scanning 6 module "clock"
hourhdis: IN INTEGER RANGE 0 TO 2;
--time information received from module "clock"
hourldis: IN INTEGER RANGE 0 TO 9;
minhdis: IN INTEGER RANGE 0 TO 5;
minldis: IN INTEGER RANGE 0 TO 9;
secldis: IN INTEGER RANGE 0 TO 9;
sechdis: IN INTEGER RANGE 0 TO 5);
PROCEDURE LEDDISP(NUMBER:INTEGER RANGE 0 TO 9) IS
--this function will transform data to format of display
BEGIN
CASE NUMBER IS
WHEN 0=>trandis<="00111111";
WHEN 1=>trandis<="00000110";
WHEN 2=>trandis<="01011011";
WHEN 3=>trandis<="01001111";
WHEN 4=>trandis<="01100110";
WHEN 5=>trandis<="01101101";
WHEN 6=>trandis<="01111101";
WHEN 7=>trandis<="00000111";
WHEN 8=>trandis<="01111111";
WHEN 9=>trandis<="01101111";
END CASE;
END LEDDISP;
END display;
ARCHITECTURE display_archi OF display IS
TYPE STATE IS (hh,hl,mh,ml,sh,sl);
--six states correspond to six led display
SIGNAL nexsta,cursta: STATE;
BEGIN
SCAN:
PROCESS(sclk)
BEGIN
if reset='1' then
nexsta<=hh;
elsif (sclk='1' and sclk'event) then
cursta<=nexsta;
end if;
CASE cursta IS
WHEN hh=>
disselect<="000";
LEDDISP(hourhdis);
nexsta<=hl;
WHEN hl=>
disselect<="001";
LEDDISP(hourldis);
nexsta<=mh;
WHEN mh=>
disselect<="010";
LEDDISP(minhdis);
nexsta<=ml;
WHEN ml=>
disselect<="011";
LEDDISP(minldis);
nexsta<=sh;
WHEN sh=>
disselect<="100";
LEDDISP(sechdis);
nexsta<=sl;
WHEN sl=>
disselect<="101";
LEDDISP(secldis);
nexsta<=hh;
WHEN others =>
null;
END CASE;
END PROCESS;
END display_archi;
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