📄 clock_1.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock_1 is
port(clk:in std_logic;----时钟输入 1khz
clr:in std_logic;----清零
en:in std_logic;-----暂停
seg:out std_logic_vector(6 downto 0);---数码管显示信号
scan:out std_logic_vector(5 downto 0));--数码管扫描信号
end;
architecture one of clock_1 is
signal qhh,qhl,qmh,qml,qsh,qsl:std_logic_vector(3 downto 0);
signal data:std_logic_vector(3 downto 0);
signal cnt:integer range 0 to 5;
signal clk1hz:std_logic;
signal sec,min:integer range 0 to 59;
signal hour:integer range 0 to 23;
begin
------------------------------------1hz分频------
process(clk)
variable count:integer range 0 to 499;
begin
if clk'event and clk='1' then
if count=499 then clk1hz<=not clk1hz;count:=0;
else count:=count+1;
end if;
end if;
end process;
-------------------------记时
process(clk1hz,clr,en,hour,min,sec)
begin
if en='1' then hour<=hour;min<=min;sec<=sec;
elsif clr='1' then hour<=0;min<=0;sec<=0;
elsif clk1hz'event and clk1hz='1' then
if sec=59 then sec<=0;
if min=59 then min<=0;
if hour=23 then hour<=0;
else hour<=hour+1;end if;
else min<=min+1;end if;
else sec<=sec+1;end if;
end if;
end process;
---------------------------秒计数的十进制转BCD码--------
process(sec)
begin
case sec is
when 0|10|20|30|40|50 =>qsl<="0000";
when 1|11|21|31|41|51 =>qsl<="0001";
when 2|12|22|32|42|52 =>qsl<="0010";
when 3|13|23|33|43|53 =>qsl<="0011";
when 4|14|24|34|44|54 =>qsl<="0100";
when 5|15|25|35|45|55 =>qsl<="0101";
when 6|16|26|36|46|56 =>qsl<="0110";
when 7|17|27|37|47|57 =>qsl<="0111";
when 8|18|28|38|48|58 =>qsl<="1000";
when 9|19|29|39|49|59 =>qsl<="1001";
when others=>null;
end case;
case sec is
when 0|1|2|3|4|5|6|7|8|9 =>qsh<="0000";
when 10|11|12|13|14|15|16|17|18|19 =>qsh<="0001";
when 20|21|22|23|24|25|26|27|28|29 =>qsh<="0010";
when 30|31|32|33|34|35|36|37|38|39 =>qsh<="0011";
when 40|41|42|43|44|45|46|47|48|49 =>qsh<="0100";
when 50|51|52|53|54|55|56|57|58|59 =>qsh<="0101";
when others=>null;
end case;
end process;
---------------------------分计数的十进制转BCD码---------
process(min)
begin
case min is
when 0|10|20|30|40|50 =>qml<="0000";
when 1|11|21|31|41|51 =>qml<="0001";
when 2|12|22|32|42|52 =>qml<="0010";
when 3|13|23|33|43|53 =>qml<="0011";
when 4|14|24|34|44|54 =>qml<="0100";
when 5|15|25|35|45|55 =>qml<="0101";
when 6|16|26|36|46|56 =>qml<="0110";
when 7|17|27|37|47|57 =>qml<="0111";
when 8|18|28|38|48|58 =>qml<="1000";
when 9|19|29|39|49|59 =>qml<="1001";
when others=>null;
end case;
case min is
when 0|1|2|3|4|5|6|7|8|9 =>qmh<="0000";
when 10|11|12|13|14|15|16|17|18|19 =>qmh<="0001";
when 20|21|22|23|24|25|26|27|28|29 =>qmh<="0010";
when 30|31|32|33|34|35|36|37|38|39 =>qmh<="0011";
when 40|41|42|43|44|45|46|47|48|49 =>qmh<="0100";
when 50|51|52|53|54|55|56|57|58|59 =>qmh<="0101";
when others=>null;
end case;
end process;
---------------------------小时计数的十进制转BCD码---------
process(hour)
begin
case hour is
when 0|10|20 =>qhl<="0000";
when 1|11|21 =>qhl<="0001";
when 2|12|22 =>qhl<="0010";
when 3|13|23 =>qhl<="0011";
when 4|14 =>qhl<="0100";
when 5|15 =>qhl<="0101";
when 6|16 =>qhl<="0110";
when 7|17 =>qhl<="0111";
when 8|18 =>qhl<="1000";
when 9|19 =>qhl<="1001";
when others=>null;
end case;
case hour is
when 0|1|2|3|4|5|6|7|8|9 =>qhh<="0000";
when 10|11|12|13|14|15|16|17|18|19 =>qhh<="0001";
when 20|21|22|23 =>qhh<="0010";
when others=>null;
end case;
end process;
----------------------------------------数码管动态扫描计数----------------------
process(clk)
begin
if clk'event and clk='1' then
if cnt=5 then cnt<=0;
else cnt<=cnt+1;
end if;
end if;
end process;
-------------------------------------数码管动态扫描-----------
process(cnt,qhh,qhl,qmh,qml,qsh,qsl)
begin
case cnt is
when 0=> data<=qsl;scan<="000001";
when 1=> data<=qsh;scan<="000010";
when 2=> data<=qml;scan<="000100";
when 3=> data<=qmh;scan<="001000";
when 4=> data<=qhl;scan<="010000";
when 5=> data<=qhh;scan<="100000";
when others=>null;
end case;
end process;
-----------------------------------------七段译码--------------------
process(data)
begin
case data is
when"0000"=>seg<="1111110";
when"0001"=>seg<="0110000";
when"0010"=>seg<="1101101";
when"0011"=>seg<="1111001";
when"0100"=>seg<="0110011";
when"0101"=>seg<="1011011";
when"0110"=>seg<="1011111";
when"0111"=>seg<="1110000";
when"1000"=>seg<="1111111";
when"1001"=>seg<="1111011";
when others=>seg<="1001111";
end case;
end process;
end;
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