lcd_driver.vhd

总体演示程序DEMO_FPGA.rar

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity lcd is
    Port ( clk   : in std_logic;	   --1khz的扫描频率；
           reset : in std_logic;
           lcdda : out std_logic;
           lcdrw : out std_logic;
           lcden : out std_logic;
		 lcd_address : out std_logic_vector(4 downto 0);
	      lcddin : in std_logic_vector(7 downto 0);
           data  : out std_logic_vector(7 downto 0));
end lcd;

architecture driver of lcd is

type state is (set_dlnf,clear_lcd,set_cursor,set_location3,write_data2,set_dcb,
set_location,write_data,write_data3,set_location2,set_cgram_location,write_cgram);
signal current_state:state;

begin
    
    lcden<=clk;
    lcdrw<='0';

controll:process(clk,reset)
variable cnt1 : integer range 0 to 31;
variable cnt2 : std_logic_vector(4 downto 0);
begin
   if reset='1'then cnt1:=0;cnt2:="00000";current_state<=set_dlnf;
   elsif falling_edge(clk)then
	 case current_state is
	 when set_dlnf=>
				 lcdda<='0';
				 data<="00111100";
				 current_state<=clear_lcd;

	 when clear_lcd=>
				 lcdda<='0';
				 data<="00000001";
				 current_state<=set_cursor;

      when set_cursor=>
				 lcdda<='0';
				 data<="00000110";
				 current_state<=set_dcb;

      when set_dcb=>
				 lcdda<='0';
				 data<="00001111";
				 current_state<=set_location;

	 when set_location=>
				 lcdda<='0';
				 data<="10000000";
				 current_state<=write_data;

      when write_data=>
				 lcdda<='1';
				 data<=lcddin;
				 cnt2:=cnt2+1;
				 if cnt2="10000" then current_state<=set_location2;
				 end if;		

      when set_location2=>
	                lcdda<='0';
				 data<="11000000";
				 current_state<=write_data2;

	 when write_data2=> 
	                lcdda<='1';
				 data<=lcddin;
				 --data<="00111001";
				 cnt2:=cnt2+1;
				 if cnt2="00000" then current_state<=set_location;
				 end if;
	
      when others=>current_state<=set_dlnf;
	 end case;
	 lcd_address<=cnt2;
   end if;
end process;
end driver;