代码搜索：1KHZ
找到约 286 项符合「1KHZ」的源代码
代码结果 286
www.eeworm.com/read/412232/11209049
c wave_cod.c
/******************************************
request:out put 1khz,10khz,100khz,1mhz
*******************************************/
#include
#include
#include
www.eeworm.com/read/343900/11920082
v lift2.v
module lift2(clk, //1KHz
reset, //reset signal,low(0) active
//maintain, //maintain signal,low(0) active
up1, //1st floor ,request for up,
www.eeworm.com/read/336234/12462477
m chirp_sine.m
function [S,A,X,Fs] = Chirp_Sine
% Chirp_Sine is used to generate the mixed signal of chirp and sine at 1kHz
% Usage:
% [S,A,X,Fs] = Chirp_Sine;
% Input: none
%Output:
% * S is the column vectors o
www.eeworm.com/read/442478/7650832
vhd leddongtai.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY leddongtai IS
PORT
(
clock :IN STD_LOGIC; --clock is 1KHZ
flash : IN STD_LOGIC;
ewh,ewl,snh,snl : IN
www.eeworm.com/read/17522/734319
vhd control_display.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity control_display is
Port (clk : in std_logic; -- 1khz;
start :
www.eeworm.com/read/17848/762346
vhd control_display.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity control_display is
Port (clk : in std_logic; -- 1khz;
start :
www.eeworm.com/read/476527/1368706
vhd control_display.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity control_display is
Port (clk : in std_logic; -- 1khz;
start :
www.eeworm.com/read/412366/11202661
bak divider.vhd.bak
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY divider IS
PORT(iCLK:in std_logic;--input,1KHz
oCLK:out std_logic);--output,1Hz
END divider;
ARCHITECTURE arch OF divider IS
SIGNAL cou
www.eeworm.com/read/412366/11202709
vhd divider.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY divider IS
PORT(iCLK:in std_logic;--input,1KHz
oCLK:out std_logic);--output,1Hz
END divider;
ARCHITECTURE arch OF divider IS
SIGNAL cou
www.eeworm.com/read/391317/8409688
vhd saomiao.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity saomiao is
port(one,ten:in std_logic_vector(3 downto 0);
clk:in std_logic;---1khz;
data:out