📄 leddongtai.vhd
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY leddongtai IS
PORT
(
clock :IN STD_LOGIC; --clock is 1KHZ
flash : IN STD_LOGIC;
ewh,ewl,snh,snl : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
leddisp : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
sel : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
dp : OUT STD_LOGIC
);
END leddongtai;
ARCHITECTURE one OF leddongtai IS
SIGNAL count : INTEGER RANGE 0 TO 4;
BEGIN
PROCESS (clock)
BEGIN
IF rising_edge(clock) THEN
IF flash = '1' THEN
count <= 4;
ELSE
IF count <3 THEN
count <= count+1;
ELSE
count <= 0;
END IF;
END IF;
CASE count IS
WHEN 0 => leddisp <= ewl; sel <= "1110";
WHEN 1 => leddisp <= ewh; sel <= "1101";
WHEN 2 => leddisp <= snl; sel <= "1011";
WHEN 3 => leddisp <= snh; sel <= "0111";
WHEN OTHERS => leddisp <= "1111111"; sel <= "1111";
END CASE;
END IF;
END PROCESS;
dp <= '1';
END one;
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